PHT4NQ10T
TrenchMOS™ standard level FET
M3D087
Rev. 02 — 2 May 2002
Product data
1. Description
N-channel enhancement mode field-effect transistor in a plastic package using
TrenchMOS™ technology.
Product availability:
PHT4NQ10T in SOT223.
2. Features
s
TrenchMOS™ technology
s
Very fast switching
s
Surface mount package.
3. Applications
s
Primary side switch in DC to DC converters
s
High speed line driver
s
Fast general purpose switch.
4. Pinning information
Table 1:
Pin
1
2
3
4
Pinning - SOT223, simplified outline and symbol
Description
gate (g)
4
Simplified outline
Symbol
d
drain (d)
source (g)
drain (d)
1
Top view
g
s
2
3
MSB002 - 1
MBB076
SOT223
Philips Semiconductors
PHT4NQ10T
TrenchMOS™ standard level FET
5. Quick reference data
Table 2:
V
DS
I
D
P
tot
T
j
R
DSon
Quick reference data
Conditions
25
°C ≤
T
j
≤
150
°C
T
sp
= 25
°C;
V
GS
= 10 V
T
sp
= 25
°C
V
GS
= 10 V; I
D
= 1.75 A
T
j
= 25
°C
T
j
= 150
°C
200
-
250
575
mΩ
mΩ
Typ
-
-
-
-
Max
100
3.5
6.9
150
Unit
V
A
W
°C
drain-source voltage (DC)
drain current (DC)
total power dissipation
junction temperature
drain-source on-state resistance
Symbol Parameter
6. Limiting values
Table 3: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
DS
V
DGR
V
GS
I
D
Parameter
drain-source voltage (DC)
drain-gate voltage (DC)
gate-source voltage (DC)
drain current (DC)
T
sp
= 25
°C;
V
GS
= 10 V;
Figure 2
and
3
T
sp
= 100
°C;
V
GS
= 10 V;
Figure 2
I
DM
P
tot
T
stg
T
j
I
S
I
SM
E
DS(AL)S
I
DS(AL)SM
peak drain current
total power dissipation
storage temperature
junction temperature
source (diode forward) current (DC)
peak source (diode forward) current
T
sp
= 25
°C
T
sp
= 25
°C;
pulsed; t
p
≤
10
µs
T
sp
= 25
°C;
pulsed; t
p
≤
10
µs;
Figure 3
T
sp
= 25
°C;
Figure 1
Conditions
25
°C ≤
T
j
≤
150
°C
25
°C ≤
T
j
≤
150
°C;
R
GS
= 20 kΩ
Min
-
-
-
-
-
-
-
−65
−65
-
-
-
-
Max
100
100
±20
3.5
2.2
14
6.9
+150
+150
3.5
14
45
3.5
Unit
V
V
V
A
A
A
W
°C
°C
A
A
mJ
A
Source-drain diode
Avalanche ruggedness
non-repetitive drain-source avalanche unclamped inductive load; I
D
= 3.5 A;
energy
t
p
= 0.2 ms; V
DD
≤
15 V; R
GS
= 50
Ω;
V
GS
= 10 V; starting T
j
= 25
°C;
peak non-repetitive drain-source
Figure 4
avalanche current
9397 750 09581
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 02 — 2 May 2002
2 of 12
Philips Semiconductors
PHT4NQ10T
TrenchMOS™ standard level FET
03aa17
120
Pder
(%)
120
I
der
(%)
80
03aa25
80
40
40
0
0
50
100
150
Tsp (°C)
200
0
0
50
100
150
200
Tsp
(°C)
P
tot
P
der
=
----------------------
×
100%
P
°
tot
(
25 C
)
V
GS
≥
10 V
I
D
I
der
=
------------------
×
100%
-
I
°
D
(
25 C
)
Fig 1. Normalized total power dissipation as a
function of solder point temperature.
Fig 2. Normalized continuous drain current as a
function of solder point temperature.
102
ID
(A)
10
Limit RDSon = VDS/ID
03aa88
10
IAS
03aa97
tp = 10
µs
100
µs
(A)
25
°C
1
1
1 ms
DC
10-1
10 ms
100 ms
Tj prior to avalanche = 125
°C
10-2
1
10
102
103
VDS (V)
10-1
10-2
10-1
1
tp (ms)
10
T
sp
= 25
°C;
I
DM
is single pulse.
Unclamped inductive load; V
DD
≤
15 V; R
GS
= 50
Ω;
V
GS
= 10 V; starting T
j
= 25
°C
and 125
°C.
Fig 3. Safe operating area; continuous and peak drain
currents as a function of drain-source voltage.
Fig 4. Non-repetitive avalanche ruggedness current
as a function of pulse duration.
9397 750 09581
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 02 — 2 May 2002
3 of 12
Philips Semiconductors
PHT4NQ10T
TrenchMOS™ standard level FET
7. Thermal characteristics
Table 4:
Symbol
R
th(j-sp)
R
th(j-a)
Thermal characteristics
Parameter
thermal resistance from junction to solder
point
Conditions
Min
Typ
-
150
Max
18
-
Unit
K/W
K/W
mounted on a metal clad substrate; -
Figure 5
thermal resistance from junction to ambient mounted on a printed circuit board; -
minimum footprint
7.1 Transient thermal impedance
102
Zth(j-sp)
(K/W)
10
δ
= 0.5
0.2
0.1
1
0.05
0.02
P
tp
T
03aa87
δ
=
10-1
single pulse
tp
T
t
10-2
10-5
10-4
10-3
10-2
10-1
1
tp (s)
10
Mounted on a metal clad substrate.
Fig 5. Transient thermal impedance from junction to solder point as a function of pulse duration.
9397 750 09581
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 02 — 2 May 2002
4 of 12
Philips Semiconductors
PHT4NQ10T
TrenchMOS™ standard level FET
8. Characteristics
Table 5: Characteristics
T
j
= 25
°
C unless otherwise specified
Symbol
V
(BR)DSS
Parameter
drain-source breakdown
voltage
Conditions
I
D
= 250
µA;
V
GS
= 0 V
T
j
= 25
°C
T
j
=
−55 °C
V
GS(th)
gate-source threshold voltage I
D
= 1 mA; V
DS
= V
GS
T
j
= 25
°C;
Figure 10
T
j
= 150
°C;
Figure 10
T
j
=
−55 °C;
Figure 10
I
DSS
drain-source leakage current
V
DS
= 100 V; V
GS
= 0 V
T
j
= 25
°C
T
j
= 150
°C
V
DS
= 60 V; V
GS
= 0 V
T
j
= 85
°C
I
GSS
R
DSon
gate-source leakage current
drain-source on-state
resistance
V
GS
=
±20
V; V
DS
= 0 V
V
GS
= 10 V; I
D
= 1.75 A
T
j
= 25
°C;
Figure 8
and
9
T
j
= 150
°C;
Figure 9
Dynamic characteristics
g
fs
Q
g(tot)
Q
gs
Q
gd
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
V
SD
t
rr
Q
r
forward transconductance
total gate charge
gate-source charge
gate-drain (Miller) charge
input capacitance
output capacitance
reverse transfer capacitance
turn-on delay time
rise time
turn-off delay time
fall time
source-drain (diode forward)
voltage
reverse recovery time
recovered charge
I
S
= 3.5 A; V
GS
= 0 V;
Figure 14
I
S
= 3.5 A;
dI
S
/dt =
−100
A/µs;
V
GS
= 0 V; V
DS
= 30 V
V
DD
= 50 V; R
D
= 15
Ω;
V
GS
= 10 V; R
G
= 6
Ω
V
GS
= 0 V; V
DS
= 25 V;
f = 1 MHz;
Figure 13
V
DS
= 5 V; I
D
= 3.5 A;
Figure 12
I
D
= 3.5 A; V
DS
= 80 V;
V
GS
= 10 V;
Figure 15
-
-
-
-
-
-
-
-
-
-
-
-
-
-
4.2
7.4
1.5
3.3
300
44
21
8
13
20
11
0.87
50
100
-
-
-
-
-
-
-
-
-
-
1.5
-
-
S
nC
nC
nC
pF
pF
pF
ns
ns
ns
ns
V
ns
nC
-
-
200
-
250
575
mΩ
mΩ
-
-
-
10
1
100
µA
nA
-
-
1
4
25
250
µA
µA
2
1.2
-
3
-
-
4
-
6
V
V
V
100
89
130
-
-
-
V
V
Min
Typ
Max
Unit
Static characteristics
Source-drain diode
9397 750 09581
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 02 — 2 May 2002
5 of 12
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