TEST
31
GND
REF
3F0
FB
REF
Phase
Freq
Det
Filter
FS
Vco and
Time Unit
Generator
4
3
2
1
32
30
29
28
2F1
2F0
GND
1F1
1F0
V
CCN
1Q0
1Q1
GND
GND
27
26
25
24
23
22
21
20
TEST
3F1
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
SKEW
SELECT
MATRIX
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
4F0
4F1
V
CCQ
V
CCN
4Q1
4Q0
GND
GND
Three Level
Select Inputs
VCCN
VCCQ
FS
VCCN
3Q1
3Q0
2Q1
1
2Q0
FB
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1
2109876543212109876543210987654321098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432
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PI6C9911 & PI6C9911E
5V High-Speed Programmable Skew
Clock Buffers -
SuperClock
Product Features
•
Four pairs of programmable skew outputs
•
User-selectable output functions:
−
Selectable skews
−
Inverted and noninverted
−
Operation at ½ and ¼ input frequency
−
Operation at 2X and 4X input frequency
•
Low skew <100ps typical same pair, 250ps max.
•
Allow REF clock input to have Spread Spectrum
modulation for EMI reduction
•
2X, 4X, ½ and ¼ outputs
•
3-level inputs for skew and output frequency control
•
External feedback, internal loop filter
•
Low cycle-to-cycle Jitter: <25ps RMS
•
Duty cycle of output clock signals: 45% min. 55% max.
•
Same pinout as Cypress CY7B9911
•
Available in 32-pin PLCC Package (J)
•
Output Operation
3.75 to 100 MHz for PI6C9911
3.75 to 125 MHz for PI6C9911E
Description
The PI6C9911 and PI6C9911E are low-skew, low jitter, 5V phase-
lock-loop (PLL) programmable skew clock drivers, for
high-performance computing and networking applications. These
parts offer user-selectable skew-control of 4 output pairs, provid-
ing the timing delays necessary to optimize high-performance
clock-distribution circuits.
Each output can be hardwired to one of nine delay or function
configurations. Delay increments are determined by the input clock
frequency and the configurations selected by the user.
The PI6C9911 and PI6C9911E allow the REF clock input to have
Spread Spectrum modulation for EMI reduction.
Both buffers are pin-compatable with Cypresss RoboClock
CY7B9911, but with improved AC/DC characteristics.
The PI6C9911 and PI6C9911E also have the same pinout as
Cypresss CY7B9911and with balanced output drive.
Logic Block Diagram
Pin Configuration
32-Pin
J
PS8451
01/27/00
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C9911 & PI6C9911E
5V High Speed Programmable Skew
Clock Buffers -
SuperClock
Pin Definitions
Signal Name
REF
FB
FS
1F0, 1F1
2F0, 2F1
3F0, 3F1
4F0, 4F1
TEST
1Q 0, 1Q 1
2Q 0, 2Q 1
3Q 0, 3Q 1
4Q 0, 4Q 1
V
CCN
V
CCQ
GND
PWR
O
I
I/O
D e s cription
Reference frequency input. This input supplies the frequency and timing
reference which all functional variation is measured.
PLL feedback input (typically connected to one of the eight outputs).
Three- level frequency range select.
See Table 1
.
Three- level function select inputs for output pair 1 (1Q 0, 1Q 1).
See Table 2
.
Three- level function select inputs for output pair 2 (2Q 0, 2Q 1).
See Table 2
.
Three- level function select inputs for output pair 3 (3Q 0, 3Q 1).
See Table 2
.
Three- level function select inputs for output pair 4 (4Q 0, 4Q 1).
See Table 2
.
Three- level select. See test mode section under the block diagram descriptions.
O utput pair 1.
See Table 2
.
O utput pair 2.
See Table 2
.
O utput pair 3.
See Table 2
.
O utput pair 4.
See Table 2
.
Power supply for output drivers.
Power supply for internal circuitry.
Ground
Block Diagram Description
Phase Frequency Detector and Filter
These two blocks accept input signals from the reference frequency
(REF) input and the feedback (FB) input and generate correction
information to control the frequency of the Voltage-Controlled
Oscillator (VCO). These blocks, along with the VCO, form a Phase-
Locked Loop (PLL) that tracks the incoming REF signal.
VCO and Time Unit Generator
The VCO accepts analog control inputs from the PLL filter block
and generates a frequency that is used by the time unit generator to
create discrete time units that are selected in the skew mix matrix.
The operational range of the VCO is determined by the FS control
pin. The time unit (t
U
) is determined by the operating frequency of
the device and the level of the FS pin as shown in Table 1.
Skew Select Matrix
The skew select matrix is comprised of four independent sections.
Each section has two low-skew, high-fanout drivers (xQ0, xQ1),
and two corresponding three-level function select (xF0, xF1)
inputs. Table 2 shows the nine possible output functions for each
section as determined by the function select inputs. All times are
measured with respect to the REF input assuming that the output
connected to the FB input has 0t
U
selected.
2
PS8451
01/27/00
t
0
+1t
U
t
0
+2t
U
t
0
+3t
U
t
0
+4t
U
t
0
+5t
U
1Fx
2Fx
(N/A)
LL
LM
LH
ML
MM
MH
HL
HM
HH
(N/A)
(N/A)
(N/A)
3Fx
4Fx
LM
LH
(N/A)
ML
(N/A)
MM
(N/A)
MH
(N/A)
HL
FB Input
REF Input
-6t
U
-4t
U
-3t
U
-2t
U
-1t
U
0t
U
+1t
U
+2t
U
+3t
U
+4t
U
HM
+6t
U
LL/HH DIVIDED
HH
INVERT
Figure 1. Typical Outputs with FB Connected to a Zero-Skew Output
(4)
3
PS8451
01/27/00
t
0
+6t
U
t
0
-6t
U
t
0
-5t
U
t
0
-4t
U
t
0
-3t
U
t
0
-2t
U
t
0
-1t
U
t
0
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21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C9911 & PI6C9911E
5V High Speed Programmable Skew
Clock Buffers -
SuperClock
Table 1. Frequency Range Select and t
U
Calculation
(1)
FS
(2,3)
f
NOM
(M Hz)
M in.
LOW
PI6C9911
MID
HIGH
LOW
PI6C9911E
MID
HIGH
15
25
40
20
35
60
M ax.
30
50
100
40
70
125
Table 2. Programmable Skew Configurations
(1)
Function Se le cts
1F1, 2F1,
3F1, 4F1
Output Functions
3Q0, 3Q1
4Q0,
4Q1
1F0, 2F0, 1Q0, 1Q1,
3F0, 4F0 2Q0, 2Q1
LOW
LOW
MID
HIGH
LOW
- 4t
U
- 3t
U
- 2t
U
- 1t
U
- 0t
U
+1t
U
+2t
U
+3t
U
+4t
U
+2t
U
+4t
U
+6t
U
Divide by 4
Inverted
t
U
=
1
f
NOM
x N
where N=
44
26
16
44
26
16
Approximate
Fre que ncy
(M Hz) at
which
t
U
= 1.0ns
22.7
38.5
62.5
22.7
38.5
Divide by 2
- 6t
U
- 4t
U
- 2t
U
MID
MID
HIGH
LOW
HIGH
62.5
MID
HIGH
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21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C9911 & PI6C9911E
5V High Speed Programmable Skew
Clock Buffers -
SuperClock
Test Mode
The TEST input is a three-level input. In normal system operation,
this pin is connected to ground, allowing the PI6C9911 to
operate as explained briefly above (for testing purposes, any of the
three-level inputs can have a removable jumper to ground, or be
tied LOW through a 100Ω resistor. This will allow an external tester
to change the state of these pins).
If the TEST input is forced to its MID or HIGH state, the device will
operate with its internal phase locked loop disconnected, and in-
put levels supplied to REF will directly control all outputs.
Relative output to output functions are the same as in normal mode.
In contrast with normal operation (TEST tied LOW). All outputs
will function based only on the connection of their own function
select inputs (xF0 and xF1) and the waveform characteristics of the
REF input.
Maximum Ratings
(Above which the useful life may be impaired)
Storage Temperature ............................................ 65ºC to +150ºC
Ambient Temperature
with Power Applied .............................................. 55ºC to +125ºC
Supply Voltage to Ground Potential ....................... 0.5V to +7.0V
DC Input Voltage .................................................... 0.5V to +7.0V
Output Current into Outputs (LOW) ................................... 64mA
Static Discharge Voltage
(per MIL-STD-883, Method 3015) ................................. >2001V
Latch-Up Current ............................................................ >200mA
Operating Range
Range
Commercial
Industrial
Ambie nt Te mpe rature
0ºC to +70ºC
40ºC to +85ºC
V
CC
5V ±10%
Notes for Tables on Pages 3 through 7:
1. For all three-state inputs, HIGH indicates a connection to V
CC
, LOW indicates a connections to GND, and MID indicates an open
connection. Internal termination circuitry holds an unconnected input to V
CC
/2.
2. The level to be set on FS is determined by the normal operating frequency (f
NOM
) of the V
CO
and the Time Unit Generator (see Logic
Block Diagram). Nominal frequency (f
NOM
) always appears at 1Q0 and the other outputs when they are operated in their undivided
modes (see Table 2). The frequency appearing at the REF and FB inputs will be f
NOM
when the output connected to FB is undivided.
The frequency of the REF and FB inputs will be f
NOM
/2 or f
NOM
/4 when the part is configured for a frequency multiplication by
using a divided output as the FB input.
3. When the FS pin is selected HIGH, the REF input must not transition upon power-up untill V
CC
has reached 4.3V.
4. FB connected to an output selected for zero skew (ie., xF1 = xF0 = MID).
6. These inputs are normally wired to V
CC
, GND, or left unconnected (actual threshhold voltages vary as a percentage of V
CC
). Internal
termination resistors hols unconnected inputs at V
CC
/2. If these inputs are switched, the function and timing of the outputs may glitch
and the PLL may require an additional t
LOCK
time before all datasheet limits are achieved.
10. Test measurement levels are TTL levels (1.5V to 1.5V). Test conditions assume signal transition times of 2ns or less and output loading as shown
in the AC Test Loads and Waveforms unless specified.
11. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters.
12. Skew is defined as the time between the earliest and the latest output transition among all outputs for which the same t
U
delay has been selected
when all are loaded with 30pF and terminated with 50Ω to 2.06V.
13. t
SKEWPR
is defined as the skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0t
U
.
14. t
SKEW0
is defined as the skew between outputs when they are selected for 0t
U
. Other outputs are divided or inverted but not shifted.
15. There are three classes of outputs: Nominal (multiple of t
U
delay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH), and Divided
(3Qx and 4Qx only in Divide-by-2 or Divide-by-4 mode).
16. t
DEV
is the output-to-output skew between any two devices operating under the same conditions (V
CC
ambient temperature, air flow, etc.).
17. t
ODCV
is the deviation of the output from a 50% duty cycle. Output pulse width variations are included in t
SKEW2
and t
SKEW4
specifications.
18. Specified with outputs loaded with 30pF. Devices are terminated through 50Ω to 2.06V.
19. t
PWH
is measured at 2.0V. T
PWL
is measured at 0.8V
20. t
ORISE
and t
OFALL
measured between 0.8V and 2.0V.
21. t
LOCK
is the time that is required before synchronization is achieved. This specification is valid only after V
CC
is stable and within normal
operating limits. This parameter is measured from the application of a new signal or frequency at REF or FB until t
PD
is within specified limits.
4
PS8451
01/27/00
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21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C9911 & PI6C9911E
5V High Speed Programmable Skew
Clock Buffers -
SuperClock
DC Characteristics Over the Operating Range
Symbol
V
OH
V
OL
V
IH
V
IL
V
IH3
V
IM3
V
IL3
I
IN
I
3
Parameter
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage of REF, FB inputs
Input LOW Voltage of REF, FB inputs
Input HIGH Voltage of 3-level inputs
TEST, FS, xFn
(6)
Input MID Voltage of 3-level inputs
TEST, FS, xFn
(6)
Input LOW Voltage of 3-level inputs
TEST, FS, xFn
(6)
Input Leakage Current of REF, FB inputs
3-Level Input DC Current
(TEST, FS, nF 1:0)
V
IN
= V
CC
or GND, V
CC
= Max
V
IN
= V
CC
(HIGH level)
V
IN
= V
CC
/2 (MID level)
V
IN
= GND (LOW level)
I
OS
I
CCQ
I
CCN
PD
Short Circuit Current
Operating Current usd by Internal
Circuitry
Output Buffer Current per Output Pair
Power Dissipation per Output Pair
V
CC
= Max. V
OUT
= GND (25°
only)
V
CCN
= V
CCQ
= Max.
All Inputs Select Open
V
CCN
= V
CCQ
= Max, I
OUT
= 0mA
Input Selects Open, f
MAX
Min
≤V
CC
≤
Max
Test Condition
Vcc = Min., I
OH
= –16mA
Vcc = Min., I
OL
= 46mA
2.0
–0.5
V
CC
–0.85V
V
CC
/2 –0.5
Min.
2.4
0.45
V
CC
0.8
V
CC
V
CC
/2
+0 . 5
0.85
10
200
50
200
–250
85
14
78
mW
mA
µΑ
V
Max.
Units
Capacitance at REF and FB
Parame te r
C
IN
De s cription
Input
Capacitance
Te s t Conditions
T
A
= 25ºC, f = 1 MHz,
V
CC
= 5.0V
M ax.
10
Units
pF
AC Test Loads and Waveforms (PI6C9911)
5V
3.0V
R1
R1 = 130
Ω
R2 = 91
Ω
2.0V
V
th
= 1.5V
0.8V
0.0V
2.0V
V
= 1.5V
th
0.8V
C
L
CL = 30pF
R2
(Includes fixture
and probe capacitance)
≤
1ns
TTL Input Test Waveform
≤
1ns
TTL AC Test Load
(16)
5
PS8451
01/27/00
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