PI6C9930S datasheet, PDF - EEWORLD Datasheet

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PI6C9930S: DescriptionPLL Based Clock Driver, 6C Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO24, 0.300 INCH, 1.27 MM PITCH, SOIC-24; Categorylogic logic; File Size330KB，6 Pages; ManufacturerPericom Semiconductor Corporation (Diodes Incorporated); Websitehttps://www.diodes.com/

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PI6C9930S Overview

PLL Based Clock Driver, 6C Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO24, 0.300 INCH, 1.27 MM PITCH, SOIC-24

PI6C9930S Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Pericom Semiconductor Corporation (Diodes Incorporated)
Parts packaging code	SOIC
package instruction	SOP, SOP24,.4
Contacts	24
Reach Compliance Code	unknown
ECCN code	EAR99
series	6C
Input adjustment	STANDARD
JESD-30 code	R-PDSO-G24
JESD-609 code	e0
length	15.4 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER
Number of functions	1
Number of inverted outputs
Number of terminals	24
Actual output times	8
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP24,.4
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
power supply	3.3 V
Prop。Delay @ Nom-Sup	0.5 ns
propagation delay (tpd)	0.5 ns
Certification status	Not Qualified
Same Edge Skew-Max（tskwd）	0.6 ns
Maximum seat height	2.65 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
width	7.5 mm
minfmax	100 MHz

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Application Note 15

Application Note15

Application of Zero Delay Buffers

in Switched Ethernet

By Cameron Katrai

Abstract

With the best and tightest characteristics of any PLL driver,

Pericom’s collection of Zero Delay Clock Drivers have found

applications in high-performance networking systems providing

clocking for devices such as FPGAs, CPUs, Switching Devices,

and Controllers. They provide the best characteristics in terms of

tight specification on skew, jitter, and phase error. The PI6C9930

(3V), PI6C2308A (3V), PI6C2501 (3V), PI6C2509A (3V),

PI6C2510A (3V), PI6C5932 (5V), and PPI6C9910 (5V) provide

multiple copies of a reference clock driven using state-of-the-art

PLL (phase-locked loop) technology. To meet both the margins

required in timing and synchronized clocking for i960 Bus and

DRAM Controller FPGA in a Switched Ethernet application, the

clock buffer must provide de-skewed clock signals. Pericom’s

PI6C2501, PI6C2308A, and PI6C2509A, for example, provide

from one to nine clock outputs with less than 200ps skew between

them and 150ps delay from input to output.

description of each member of the system and the use of Zero

Delay PLL, in conjunction with the application, follows. This note

also focuses on providing completely deskewed (zero delay) clocks

for higher speed systems (80 MHz or more) using a PLL driver

such as the PI6C2501 combined with a Buffer such as the

PI6C3813A.

Switch Analysis

Switched Ethernet makes the hub intelligent by reducing the num-

ber of ports to which data is repeated. A switching hub is more

intelligent in processing data. The hub basically buffers the data

packets that are returned as a result of simultaneous transmission

(collision). Although there is a delay resulting from buffering,

with a switching hub, the two packets can now be transmitted in

parallel. A switching hub must maintain two buffers or queues for

each of its parts. These are the input buffers and output destina-

tion. The packets in a port’s input buffer are analyzed and then

copied to the destination port’s output buffer. To rout a packet, the

destination address of a packet is compared against the known

device addresses. The packet is then entered in the destination

port’s output buffer.

The Hub can discard packets it receives when the switching hub’s

buffer memory is exhausted. This will cause those packets to be

transmitted at a later time. When a packet is discarded, the upper

layer network protocols detect a missing packet and request re-

transmission. A switching hub with a large buffer memory is more

efficient. Figure 1 depicts the block diagram of a Switched Ethernet

Hub. The design is based on Galileo Technology GT-48001

Switched Ethernet Controller and the i960 processor from Intel.

While the GT-48001 provides the Ethernet Switching functions

(inside the 8-port Switch), the i960 processor from Intel provides

the network management and control function. The block diagram

of the 8-Port Switch is shown in Figure 2.

Introduction

Switched Ethernet versus Repeater

Before the introduction of Switching Hubs, the nature of limita-

tion in repeaters was related to the nature of shared access; when

one user talks, everyone listens. In a switching system, messages

pass only to those clients who need them. The most important

point about a Switch is that it only sends packets where they need

to go. In contrast, a repeater forwards all packets to all links, wasting

a lot of bandwidth. The main advantage of a switch is its ability to

simultaneously receive multiple packets. A repeater cannot.

A repeater blocks the traffic by sending the data to all ports. While

the Switch keeps the other lines clear, it can simultaneously re-

ceive data on many ports. Transferring all packets into memory

inside the Switch does this. This application note discusses the

use of Zero Delay PLL buffers in Switched Ethernet Systems and

explains the block diagram of a Switched Ethernet system. A

12/18/98

PI6C9930S Related Products

	PI6C9930S	PI6C2510A-134	PI6C5932Q	PI6C9930H
Description	PLL Based Clock Driver, 6C Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO24, 0.300 INCH, 1.27 MM PITCH, SOIC-24	PLL Based Clock Driver, 6C Series, 10 True Output(s), 0 Inverted Output(s), PDSO24, PLASTIC, TSSOP-24	PLL Based Clock Driver, 6C Series, 6 True Output(s), 0 Inverted Output(s), CMOS, PDSO20, 0.150 INCH, 0.635 MM PITCH, QSOP-20	PLL Based Clock Driver, 6C Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO24, 5.30 MM, 0.65 MM PITCH, SSOP-24
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible
Parts packaging code	SOIC	TSSOP	QSOP	SSOP
package instruction	SOP, SOP24,.4	TSSOP,	SSOP, SSOP20,.25	SSOP, SSOP24,.3
Contacts	24	24	20	24
Reach Compliance Code	unknown	compli	unknown	unknown
ECCN code	EAR99	EAR99	EAR99	EAR99
series	6C	6C	6C	6C
Input adjustment	STANDARD	STANDARD	STANDARD	STANDARD
JESD-30 code	R-PDSO-G24	R-PDSO-G24	R-PDSO-G20	R-PDSO-G24
JESD-609 code	e0	e0	e0	e0
length	15.4 mm	7.8 mm	8.65 mm	8.2 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER
Number of functions	1	1	1	1
Number of terminals	24	24	20	24
Actual output times	8	10	6	8
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	SOP	TSSOP	SSOP	SSOP
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE, SHRINK PITCH
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Same Edge Skew-Max（tskwd）	0.6 ns	0.2 ns	0.5 ns	0.6 ns
Maximum seat height	2.65 mm	1.2 mm	1.75 mm	2 mm
Maximum supply voltage (Vsup)	3.6 V	3.6 V	5.25 V	3.6 V
Minimum supply voltage (Vsup)	3 V	3 V	4.75 V	3 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V	5 V	3.3 V
surface mount	YES	YES	YES	YES
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)	TIN LEAD	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	1.27 mm	0.65 mm	0.635 mm	0.65 mm
Terminal location	DUAL	DUAL	DUAL	DUAL
width	7.5 mm	4.4 mm	3.9116 mm	5.3 mm
Encapsulate equivalent code	SOP24,.4	-	SSOP20,.25	SSOP24,.3
power supply	3.3 V	-	5 V	3.3 V
technology	CMOS	-	CMOS	CMOS
minfmax	100 MHz	-	133 MHz	100 MHz

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