21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6CV850
2.5-V Phase Lock Loop Clock Driver
with I
2
C Control Interface
Features
Phase-Lock Loop Clock Driver for Double Data Rate
Synchronous DRAM Applications
Spread Spectrum Clock Compatible
Operating Frequency: 60 to 170 MHz
Low Jitter (cycle-cycle): <|75ps|
Distributes One Differential Clock Input to Ten
Differential Outputs
I
2
C Serial Interface Provides Output Enable and
Functional Control
Three-State Outputs when I
2
C low-level control
bit is written
Operates from dual 2.5-V and 3.3 V Supplies
External Feedback Pins (FBIN,FBIN) are used to
Synchronize the Outputs to the Input Clocks
Low Jitter < 100ps
Low Skew < 100ps
Low Phase Offset: TBD
48-Pin TSSOP Package
Description
PI6CV850 is a high-performance, low-skew, low-jitter zero-delay buffer
that distributes a differential clock input pair (CLK, CLK) to ten
differential pair of clock outputs (Y[0:9], Y[0:9]) and one differential pair
feedback clock output (FBOUT,FBOUT). Clock outputs are controlled
by input clocks (CLK, CLK), feedback clocks (FBIN,FBIN), I
2
C Control
Interface, and Analog Power input (AV
DD
). I
2
C Control Interface can
3-state individual output clock pairs. When AV
DD
is strapped LOW,
PLL is turned off and bypassed for test purposes.
The device provides a standard mode (100kbits/s) I
2
C serial interface
for device control. Implementation is as a slave/receiver, and address
is specified in I
2
C device address table. Both I
2
C inputs (SDATA &
SCLK) provide integrated pullup resistors (typically 140 kohms) .
Two 8-bit I
2
C registers provide individual enable control for each
output pair. At powerup, all outputs default to enabled . Each pair can
be placed in a 3-state mode with a low-level output when a low-level
control bit is written to the control register. Registers must be accessed
in sequence (random access of the registers not supported).
For reduced EMI, the PI6CV850 also tracks Spread Spectrum
Clocking .
Since the PI6CV850 is based on PLL circuitry, it requires a stabili-
zation time to achieve phase-lock of the PLL. This stabilization time
is required following power up. Also required are changes to
various I
2
C controls that effect the PLL.
Y0
Y0
Y1
Y1
Block Diagram
SCLK
SDATA
AVDD
Test and
Logic
3
2
5
6
10
9
20
19
22
23
46
47
44
43
39
40
29
Pin Configuration
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
GND
Y5
Y5
VDDQ
Y6
Y6
GND
GND
Y7
Y7
VDDQ
SDATA
FBIN
FBIN
VDDQ
FBOUT
FBOUT
GND
Y8
Y8
VDDQ
Y9
Y9
GND
Y0
Y0
VDDQ
Y1
Y1
GND
GND
Y2
Y2
VDDQ
SCLK
CLK
CLK
VDDI2C
AVDD
AGND
GND
Y3
Y3
Y2
Y2
Y3
Y3
Y4
Y4
Y5
Y5
Y6
Y6
Y7
Y7
Y8
Y8
48-Pin
A
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
CLK
CLK
FBIN
FBIN
13
14
36
35
30
PLL
27
26
Y9
Y9
VDDQ
Y4
Y4
GND
32 FBOUT
33 FBOUT
1
PS8481B
01/15/02
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6CV850
2.5-V Phase Lock Loop Clock Driver
with I
2
C Control Interface
Pinout Table
Pin Name
CLK
CLK
Yx
Yx
FBO UT
FBO UT
FBIN
FBIN
V
DDQ
AV
DD
Pin No.
13
14
3,5,10,20,22,27,
29,39,44,46
2,6,9,19,23,26,
30,40,43,47
33
32
35
36
4,11,21,
28,34,38,45
16
I
Power
I/O Type
I
O
Reference Clock input
Clock outputs.
Complement Clock outputs.
Feedback output.
Feedback input.
Power Supply for I/O . 2.5Volts
Analog /core power supply. AV
C C
can be used to bypass the PLL for testing
purposes. When AV
CC
is strapped to ground, PLL is bypassed and CLK is buffered
directly to the device outputs. 2.5Volts
Ground
Analog/core ground. Provides the ground reference for the analog/core circuitry
Ground
Serial Data in for Serial Configuration port
Clock Input for Serial Configuration port
2.5V or 3.3V Supply for I
2
C Interface
D e s cription
AGND
GND
SDATA
SCLK
V
DDI2C
17
1,7,8,18,24,25,
31,41,42,48
37
12
15
I
2
C
Power
Absolute Maximum Ratings
(Over operating free-air temperature range)
Symbol
V
DDQ
, AV
CC
V
I
V
O
Tstg
Parame te r
I/O supply voltage range and analog/core supply voltage range
Input voltage range
Output voltage range
Storage temperature
M in.
0.5
0.5
0.5
65
M ax.
3.6
V
DDQ
+0.5
150
V
Units
o
C
Stress beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
2
PS8481B
01/15/02
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6CV850
2.5-V Phase Lock Loop Clock Driver
with I
2
C Control Interface
DC Specifications
Symbol
AV
CC
V
DDQ
V
IL
V
IH
V
OH
V
OL
V
IX
V
OX
V
IN
V
ID
V
DD
I
2
C
V
OD
T
A
Recommended Operating Conditions
Parame te r
Analog/core supply voltage
Output supply voltage
Low- level input voltage for I
2
C
High- level input voltage for I
2
C
High- level output voltage, I
OL
= 12mA
Low- level output voltage, I
OL
= 12mA
Input differential- pair crossing voltage
Output differential- pair crossing voltage
at the DRAM clock input
Input voltage level
Input differential voltage between CK and CK
2.5V or 3.3V for I
2
C supply
Output differential voltage
Operating free air temperature
M in.
2.3
2.3
Vss 0.3
2.0
1.7
0
(V
DDQ
/2) 0.2
(V
DDQ
/2) 0.2
0.3
0
2.3
0.7
0
Nom.
2.5
2.5
M ax.
2.7
2.7
0.8
V
DDQ
+0.3
V
DDQ
0.6
(V
DDQ
/2) +0.2
(V
DDQ
/2) +0.2
V
DDQ
+0.3
0.71
3.6
V
DDQ
+0.6
70
°C
Units
V
Electrical Characteristics
Parame te r
V
IK
I
I
I
DDQ
C
I
All inputs
CK, FBIN
SDATA, SCLK
Dynamic supply current
CK and CK
FBIN and FBIN
V
I
= V
DD
or GND
2.5V
2.0
Te s t Conditions
I
I
= 18mA
V
I
= V
DDQ
or GND
V
I
= V
DDQ
or GND
2.7V
A
VCC
, V
DDQ
2.3V
M in.
Typ.
M ax.
1.2
±10
±5
300
3.0
Units
V
m
A
mA
pF
3
PS8481B
01/15/02
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6CV850
2.5-V Phase Lock Loop Clock Driver
with I
2
C Control Interface
Timing Requirements
(Over recommended operating free-air temperature).
A
VCC
, V
DDQ
= 2.5V ±0.2V
Symbol
f
CK
t
DC
t
STAB
De s cription
Operating clock frequency
(1,2)
Application clock frequency
(3)
Input clock duty cycle
PLL stabilization time after powerup
M in.
60
95
40
M ax.
170
170
60
100
MHz
%
Units
m
s
Notes:
1. The PLL is able to handle spread spectrum induced skew.
2. Operating clock frequency indicates a range over which the PLL is able to lock, but in which the clock is not
required to meet the other timing parameters. (Used for low-speed debug).
3. Application clock frequency indicates a range over which the PLL meets all of the timing parameters.
AC Specifications
Switching characteristics over recommended Operating free-air temperature range (unless otherwise noted)
AV
CC
, V
D D Q
= 2.5V ±0.2V
Parame te r
tjit(cc)
t(
q
)
tsk(o)
tjit(per)
tjit(hper)
tsl(i)
tsl(o)
De s cription
Cycle- to- cycle jitter
Static phase error
(1)
Output clock skew
Period jitter
Half- period jitter
Input clock slew rate
(2)
Output clock slew rate
(2)
Diagram
see Figure 3
see Figure 4
see Figure 5
see Figure 6
see Figure 7
see Figure 8
see Figure 8
75
100
1.0
1.0
M in.
75
0
100
75
100
2.0
2.0
V/ns
ps
Nom.
M ax
75
Units
The PLL on the PI6CV850 meets all the above parameters while supporting SSC synthesizers
(3)
with the following parameters.
SSC modulation frequency
SSC clock input frequency deviation
PLL loop bandwidth
Phase angle
Notes:
1. Static Phase Error does not include Jitter.
2. The slew rate is determined from the IBIS model and not from the test load.
3. The SSC requirements meet the Intel PC100 SDRAM Registered DIMM specification.
30.00
0.00
2
50.00
0.50
kHz
%
MHz
0.031
degrees
4
PS8481B
01/15/02
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6CV850
2.5-V Phase Lock Loop Clock Driver
with I
2
C Control Interface
Function Tables
INPUTS
AV
DD
GND
GND
2.5V (nom)
2.5V (nom)
CLK
L
H
L
H
CLK
H
L
H
L
Select Functions
OUTPUTS
Y[0:9]
L
H
L
H
Y[0:9]
H
L
H
L
FBOUT
L
H
L
H
FBOUT
H
L
H
L
PLL
Bypassed/Off
Bypassed/Off
On
On
Each output pair can be 3-state via the I
2
C interface, except FBOUT and FBOUT
I
2
C Device Address
A7
1
A6
1
A5
0
The following section describes the I2C interface programming.
A4
1
A3
0
A2
0
A1
1
A0
0
Writing to the I
2
C Interface
1. Send the address D2
(H)
2. Send the dummy bytes and command code.
3. Send the number of data bytes.
Clock Generator
Addr (7 bits)
A(6:0)&
R/W#
D2
(H)
ACK
+8- Bits dummy
command code
ACK
+8- Bits
dummy
ACK
Data Byte 1
ACK
Data Byte 4
ACK
I
2
C Configuration Command Bitmap
Byte 0: Enable/Disable Register
(H=Enable, L=Disable)
Byte 1: Enable/Disable Register
(H=Enable, L=Disable)
Bit
7
6
5
4
3
2
1
0
Pins
3,2
5,6
10,9
20,19
22,23
46,47
44,43
39,40
PWD
De s cription
Y0,Y0
Y1,Y1
Y2,Y2
Bit
7
6
5
4
3
2
1
0
Pins
29,30
27,26
PWD
De s cription
Y8,Y8
Y9,Y9
H
Y3,Y3
Y4,Y4
Y5,Y5
Y6,Y6
Y7,Y7
H
Reserved
Note:
Disable/Output held HiZ.
5
Note:
Disable/Output held HiZ.
PS8481B
01/15/02
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