PI6CV855-02L datasheet, PDF - EEWORLD Datasheet

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PI6CV855-02L: DescriptionPLL Based Clock Driver, 6C Series, 5 True Output(s), 0 Inverted Output(s), CMOS, PDSO28, 0.173 INCH, TSSOP-28; Categorylogic logic; File Size173KB，9 Pages; ManufacturerPericom Semiconductor Corporation (Diodes Incorporated); Websitehttps://www.diodes.com/

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PI6CV855-02L Overview

PLL Based Clock Driver, 6C Series, 5 True Output(s), 0 Inverted Output(s), CMOS, PDSO28, 0.173 INCH, TSSOP-28

PI6CV855-02L Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Pericom Semiconductor Corporation (Diodes Incorporated)
Parts packaging code	SSOP
package instruction	TSSOP, TSSOP28,.25
Contacts	28
Reach Compliance Code	compliant
ECCN code	EAR99
series	6C
Input adjustment	DIFFERENTIAL
JESD-30 code	R-PDSO-G28
JESD-609 code	e0
length	9.7 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER
Humidity sensitivity level	1
Number of functions	1
Number of inverted outputs
Number of terminals	28
Actual output times	5
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Encapsulate equivalent code	TSSOP28,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	240
power supply	2.5 V
Certification status	Not Qualified
Same Edge Skew-Max（tskwd）	0.1 ns
Maximum seat height	1.2 mm
Maximum supply voltage (Vsup)	2.7 V
Minimum supply voltage (Vsup)	2.3 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
width	4.4 mm

PI6CV855-02L Preview

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PI6CV855-02

200 MHz SSTL_2 PLL Clock Driver

Features

• PLL clock distribution optimized for SSTL_2

• Distributes one differential clock input pair to five differential

clock output pairs.

• Inputs (CLK,CLK) and (FBIN,FBIN): SSTL_2

• Outputs (Yx, Yx), (FBOUT, FBOUT): SSTL_2

• External feedback pins (FBIN,FBIN) are used to

synchronize the outputs to the input clocks.

• Operates at AV

= 2.5V for core circuit and internal PLL,

and V

DDQ

= 2.5V for differential output drivers

• Packaging (Pb-free & Green available):

- 28-pin TSSOP (L28)

Description

The PI6CV855-02 PLL Clock Buffer is designed for 2.5 V

DDQ

and 2.5V

operation and differential data input and output levels. The

device is a zero delay buffer that distributes a differential clock input

pair (CLK, CLK) to five differential pairs of clock outputs (Y[0:4],

Y[0:4]) and one differential pair feedback clock outputs (FBOUT,

FBOUT). The clock outputs are controlled by the input clocks (CLK,

CLK), the feedback clocks (FBIN,FBIN), and the Analog Power input

(AV

). When the AV

is strapped low, the PLL is turned off and

bypassed for test purposes.

The PI6CV855-02 is able to track Spread Spectrum Clocking to reduce

EMI.

Block Diagram

Pin Configuration

CLK

FBIN

GND

VDDQ

CLK

AVDD

AGND

GND

VDDQ

GND

FBOUT

VDDQ

FBIN

GND

VDDQ

GND

PLL

28-Pin

Logic

and

Test Ciruit

FBOUT

PS8749A

09/16/04

21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321

PI6CV855-02

200 MHz SSTL_2 PLL Clock Driver

Pinout Table

Name

CLK

Y[0:4]

FBOUT

FBIN

DDQ

AGND

GND

Pin No.

3,11,13,17,27

2,10,14,16,28

4,12,18,22,26

1,9,15,19,25

I/O

Type

Reference Clock input

Clock outputs.

Complement Clock outputs.

Feedback output, and Complement Feedback Output

Feedback input, and Complement Feedback input

Power Supply for I/O pins.

Power Analog/core power supply. AV can be used to bypass the PLL for testing purposes. When

is strapped to ground, PLL is bypassed & CLK is buffered directly to the device outputs.

Ground

Analog/core ground. Provides the ground reference for the analog/core circuitry

Ground for I/O pins.

De s cription

Function Table

Inputs

GND

2.5V(nom)

CLK

Y[0:4]

Outputs

FBOUT

Bypassed/Off

PLL State

PS8749A

09/16/04

21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321

PI6CV855-02

200 MHz SSTL_2 PLL Clock Driver

Absolute Maximum Ratings

(Over operating free-air temperature range)

Symbol

DDQ

, AV

Tstg

Parame te r

I/O supply voltage range and analog/core supply voltage range

Input voltage range

Output voltage range

Storage temperature

M in.

– 0.5

– 65

DDQ

+0.5

M a x.

3.6

Units

150

Note:

Stress beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.

Timing Requirements

(Over recommended operating free-air temperature)

Symbol

De s cription

Operating clock frequency

(1,2)

Application clock frequency

Input clock duty cycle

PLL stabilization time after powerup

(3)

, V

DDQ

= 2.5V ±0.2V

M in.

100

M a x.

200

10 0

Units

STAB

MHz

µs

Notes:

1. The PLL is able to handle spread spectrum induced skew.

2. Operating clock frequency indicates a range over which the PLL is able to lock, but in which the clock is

not required to meet the other timing parameters. (Used for low-speed debug).

3. Application clock frequency indicates a range over which the PLL meets all of the timing parameters.

PS8749A

09/16/04

21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321

PI6CV855-02

200 MHz SSTL_2 PLL Clock Driver

DC Specifications

Recommended Operating Conditions

Symbol

DDQ

Analog/core supply voltage

Output supply voltage

High- level output voltage

Low- level output voltage

Input differential- pair crossing voltage

Output differential- pair crossing voltage at the SDRAM clock input

Input voltage level

Input differential voltage between CLK and CLK

Output differential voltage between Y[n] and Y[n] and FBOUT

and FBOUT

Operating free air temperature

Parame te r

M in.

2.3

1.8

DDQ

/2) –0.2

DDQ

/2) –0.2

–0 . 3

0.36

0.7

Nom.

2.5

M ax.

2.7

DDQ

0.5

DDQ

/2) +0.2

DDQ

/2) +0.2

DDQ

+0.3

DDQ

+0.6

DDQ

+0.6

°C

Units

Electrical Characteristics

Parame te r

DDQ

ADD

All inputs

CLK, FBIN

Dynamic supply current of V

DDQ

Dynamic supply current of AV

CLK and CLK

FBIN and FBIN

Te s t Conditions

= –18mA

= V

DDQ

or GND

= 2.7V

(1)

= 2.7V

(1)

= V

or GND

2.5V

2.0

VDD

, V

DDQ

2.3V

2.7V

M in.

Typ.

M ax.

–1.2

±10

300

3.0

Units

µA

Notes:

1. Driving memory chips with 120 Ohm termination resistor for each clock output pair at 134 MHz.

PS8749A

09/16/04

21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321

PI6CV855-02

200 MHz SSTL_2 PLL Clock Driver

AC Specifications

Switching characteristics over recommended operating free-air temperature range, f

CLK

> 100 MHz (unless otherwise noted).

(See Figure 1 and 2)

Parame te r

θ)

tjit(cc)

tjit(per)

tjit(hper)

tsl(i)

tsl(o)

tsk(o)

De s cription

Static phase offset

(1)

Cycle- to- cycle jitter

Period jitter

Half- period jitter

Input clock slew rate

(2)

Output clock slew rate

(2)

Output clock skew

Diagram

Figure 4

Figure 3

Figure 6

Figure 7

Figure 8

Figure 5

, V

D D Q

= 2.5V ±0.2V

M in.

–50

–75

–100

1.0

Nom.

M ax

100

2.0

10 0

Units

V/ns

The PLL meets all the above parameters while supporting SSC synthesizers with the following parameters

(3)

SSC modulation frequency

SSC clock input frequency deviation

PLL loop bandwidth

Phase angle

Notes:

1. Static Phase offset does not include jitter.

2. The slew rate is determined from the IBIS model with test load shown in Figure 1.

3. The SSC requirements meet the Intel PC100 SDRAM Registered DIMM specification.

30.0

0.00

50.0

–0.50

kHz

MHz

–0.031

degrees

PS8749A

09/16/04

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