21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6CV857
PLL Clock Driver for
2.5V DDR-SDRAM Memory
Product Features
PLL clock distribution optimized for Double Data Rate
SDRAM applications.
Distributes one differential clock input pair to ten differential
clock output pairs.
Inputs (CLK,CLK) and (FBIN,FBIN): SSTL_2
Input PWRDWN: LVCMOS
Outputs (Yx, Yx), (FBOUT, FBOUT): SSTL_2
External feedback pins (FBIN,FBIN) are used to
synchronize the outputs to the clock input.
Operates at AV
CC
= 2.5V for core circuit and internal PLL,
and V
DDQ
= 2.5V for differential output drivers
Package:
Plastic 48-pin TSSOP
Product Description
PI6CV857 PLL clock device is developed for registered DDR DIMM
applications This PLL Clock Buffer is designed for 2.5 V
DDQ
and 2.5V
AV
CC
operation and differential data input and output levels.
Package options include plastic Thin Shrink Small-Outline Package
(TSSOP).The device is a zero delay buffer that distributes a differ-
ential clock input pair (CLK, CLK) to ten differential pairs of clock
outputs (Y[0:9], Y[0:9]) and one differential pair feedback clock
outputs (FBOUT,FBOUT) . The clock outputs are controlled by the
input clocks (CLK, CLK), the feedback clocks (FBIN,FBIN), the 2.5V
LVCMOS input (PWRDWN) and the Analog Power input (AV
CC
).
When input PWRDWN is low while power is applied, the input
receivers are disabled, the PLL is turned off and the differential clock
outputs are 3-stated. When the AV
CC
is strapped low, the PLL is
turned off and bypassed for test purposes.
When the input frequency falls below a suggested detection fre-
quency that is below the operating frequency of the PLL, the device
will enter a low power mode. An input frequency detection circuit will
detect the low frequency condition and perform the same low power
features as when the PWRDWN input is low.
The PLL in the PI6CV857 clock driver uses input clocks (CLK, CLK)
and feedback clocks (FBIN,FBIN) to provide high-performance, low-
skew, low-jitter output differential clocks (Y[0:9], Y[0:9]). PI6CV857
is also able to track Spread Spectrum Clocking for reduced EMI.
Block Diagram/Pin Configuration
Y0
CLK
CLK
FBIN
FBIN
PLL
Y0
Y1
Y1
Y2
Y2
Y3
Y3
Y4
Y4
Y5
Powerdown
and Test
Logic
Y5
Y6
Y6
Y7
Y7
Y8
Y8
Y9
Y9
FBOUT
FBOUT
GND
Y0
Y0
VD D Q
Y1
Y1
GND
GND
Y2
Y2
VD D Q
VD D Q
CK
CK
VD D Q
AV D D
AG N D
GND
Y3
Y3
VD D Q
Y4
Y4
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
GND
Y5
Y5
VD D Q
Y6
Y6
GND
GND
Y7
Y7
VD D Q
P W R DW N
FBIN
FBIN
VD D Q
FBOUT
FBOUT
GND
Y8
Y8
VD D Q
Y9
Y9
GND
48-Pin
A
PWRDWN
AVDD
1
PS8464B
11/10/00
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6CV857
PLL Clock Driver For 2.5V DDR-SDRAM Memory
Pinout Table
Pin Name
CLK
CLK
Yx
Yx
FBOUT
FBOUT
FBIN
FBIN
Pin No.
13
14
3,5,10,20,22,27,29,39,44,46
2,6,9,19,23,26,30,40,43,47
32
33
36
35
I
PWRDWN
37
O
I/O Type
I
Reference Clock input
Clock outputs.
Complement Clock outputs.
Feedback output, and Complement Feedback Output
Feedback output, and Complement Feedback Output
Power down and output disable for all Yx and Yx outputs. When PWRDWN =
0, the part is powered down and the differential clock outputs are disabled to a
3- state. When PWRDWN = 1, all differential clock outputs are enabled and run
at the same frequency as CLK.
Power Supply for I/O.
Power
Analog /core power supply. AV
DD
can be used to bypass the PLL for testing
purposes. When AV
DD
is strapped to ground, PLL is bypassed and CLK is
buffered directly to the device outputs.
Analog/core ground. Provides the ground reference for the analog/core circuitry
Ground
De s cription
V
DDQ
AV
DD
AGND
GND
4,11,12,15,21,28,34,38,45
16
17
1,7,8,18,24,25,31,41,42,48
Ground
Function Table
Inputs
AV
DD
GND
GND
X
X
2.5V(nom)
2.5V(nom)
2.5V(nom)
G
H
H
L
L
H
H
X
CLK
L
H
L
H
L
H
CLK
H
L
H
L
H
L
Y
L
H
Z
Z
L
H
Z
Y
H
L
Z
Z
H
L
Z
Outputs
FBOUT
L
H
Z
Z
L
H
Z
FBOUT
H
L
Z
Z
H
L
Z
Bypassed/off
Bypassed/off
off
off
on
on
off
PLL State
<20 MHz
(1)
Notes:
For testing and power saving purposes, PI6CV857 will power down if the frequency of the reference inputs
CLK, CLK is well below the operating frequency range. The maximum power down clock frequency is below 20 MHz.
For example, PI6CV857 will be powered down when the CLK,CLK stop running.
Z = High impedance
X = Dont care
2
PS8464B
11/10/00
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6CV857
PLL Clock Driver For 2.5V DDR-SDRAM Memory
Absolute Maximum Ratings
(Over operating free-air temperature range)
Symbol
V
DDQ
, AV
DD
V
I
V
O
Tstg
Parame te r
I/O supply voltage range and analog/core supply voltage range
Input voltage range
Output voltage range
Storage temperature
M in.
0.5
0.5
0.5
65
M ax.
3.6
V
DDQ
+0.5
150
V
Units
o
C
Note:
Stress beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
Timing Requirements
(Over recommended operating free-air temperature)
Symbol
D e s cription
O perating clock frequency
(1,2)
Application clock frequency
Input clock duty cycle
PLL stabilization time after powerup
(3)
AV
DD
, V
DDQ
= 2.5V ±0.2V
M in.
60
95
40
M ax.
170
170
60
100
Units
f
CK
t
DC
t
STAB
MHz
%
ms
Notes:
1. The PLL is able to handle spread spectrum induced skew.
2. Operating clock frequency indicates a range over which the PLL is able to lock, but in which the clock is not required to meet the
other timing parameters. (Used for low-speed debug).
3. Application clock frequency indicates a range over which the PLL meets all of the timing parameters.
3
PS8464B
11/10/00
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6CV857
PLL Clock Driver For 2.5V DDR-SDRAM Memory
DC Specifications
Recommended Operating Conditions
Symbol
AV
DD
V
DDQ
V
IL
V
IH
V
OH
V
OL
V
IX
V
OX
V
IN
V
ID
T
A
Analog/core supply voltage
Output supply voltage
Low- level input voltage for PWRDWN pin
High- level input voltage for PWRDWN pin
High- level output voltage
Low- level output voltage
Input differential- pair crossing voltage
Output differential- pair crossing voltage at the DRAM clock input
Input voltage level
Input differential voltage between CK and CK
Operating free air temperature
Parame te r
M in.
2.3
2.3
0.3
1.7
2.0
0
(V
DDQ
/2) 0.2
(V
DDQ
/2) 0.2
0.3
0.36
0
Nom.
2.5
2.5
M ax.
2.7
2.7
0.7
V
DDQ
+0.3
V
DDQ
0.5
(V
DDQ
/2) +0.2
(V
DDQ
/2) +0.2
V
DDQ
+0.3
V
DDQ
+0.6
70
°C
V
Units
Electrical Characteristics
Parame te r
V
IK
I
I
All inputs
CK , FBIN
PWRDWN
I
DDQ
Dynamic supply current of V
DDQ
Static supply current
Dynamic supply current of AV
DD
I
ADD
Static supply current
CK and CK
FBIN and FBIN
Te s t Conditions
I
I
= 18mA
V
I
= V
DDQ
or GND
V
I
= V
DDQ
or GND
V
DD
= 2.7V
(1)
CK & CK <20 MHz or
PWRDWN = Low
(2)
V
DD
= 2.7V
(1)
CK & CK <20 MHz or
PWRDWN = Low
(2)
V
I
= V
DD
or GND
2.5V
2.0
2.7V
A
VDD
, V
DDQ
2.3V
M in.
Typ.
M ax.
1.2
±10
300
100
12
100
3.0
Units
V
µA
mA
µA
mA
µA
pF
C
I
Notes:
1. Driving 9 or 18 DDR SDRAM memory chips with 120-ohm termination resistor for each clock output pair at 134 MHz.
2. The maximum power down clock frequency is below 20 MHz.
4
PS8464B
11/10/00
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6CV857
PLL Clock Driver For 2.5V DDR-SDRAM Memory
Switching characteristics over recommended operating free-air temperature range (unless otherwise noted)
AC Specifications
Parame te r
tjit(cc)
t(
θ)
tsk(o)
tjit(per)
tjit(hper)
tsl(i)
tsl(o)
De s cription
Cycle- to- cycle jitter
Static phase offset
(1)
Output clock skew
Period jitter
Half- period jitter
Input clock slew rate
(2)
Output clock slew rate
(2)
Diagram
see Figure 3
see Figure 4
see Figure 5
see Figure 6
see Figure 7
see Figure 8
see Figure 8
AV
CC
, V
DDQ
= 2.5V ±0.2V
M in.
75
80
75
100
1.0
1.0
0
Nom.
M ax
75
80
100
75
100
2.0
2.0
Units
ps
V/ns
The PLL on the PI6CV857 is capable of meeting all the above parameters while supporting SSC synthesizers
with the following parameters
(3)
.
SSC modulation frequency
SSC clock input frequency deviation
PLL loop bandwidth
Phase angle
Notes:
1. Static Phase offset does not include Jitter.
2. The slew rate is determined from the IBIS model and not from the test load.
3. The SSC requirements meet the Intel PC100 SDRAM Registered DIMM specification.
30.00
0.00
2
50.00
0.50
0.031
kHz
%
MHz
degrees
5
PS8464B
11/10/00
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