PI74ALVCH16270
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
12-Bit To 24-Bit Registered Bus Exchanger
with 3-State Outputs
Product Description
Product Features
· PI74ALVCH16270 is designed for low voltage operation
· V
CC
= 2.3V to 3.6V
· Hysteresis on all inputs
· Typical V
OLP
(Output Ground Bounce)
< 0.8V at V
CC
= 3.3V, T
A
= 25°C
· Typical V
OHV
(Output V
OH
Undershoot)
< 2.0V at V
CC
= 3.3V, T
A
= 25°C
· Bus Hold retains last active bus state during 3-STATE,
eliminating the need for external pullup resistors
· Industrial operation at –40°C to +85°C
· Packages available:
– 56-pin, 240-mil wide plastic TSSOP (A)
– 56-pin, 300-mil wide plastic SSOP (V)
Pericom Semiconductor’s PI74ALVCH series of logic circuits are
produced in the Company’s advanced 0.5 micron CMOS technology,
achieving industry leading speed.
The PI7ALVCH16270 is used in applications where data must
be transferred from a narrow high-speed bus to a wider lower
frequency bus.
The device provides synchronous data exchange between the two
ports. Data is stored in the internal registers on the
low-to-high transition of the clock (CLK) input when the appropriate
CLKEN inputs are low. The select (SEL) line selects 1B or 2B data
for the A outputs. For data transfer in the A-to-B direction, a two
stage pipeline is provided in the A-to1B path,with a single storage
register in the A-to-2B path. Proper control of the CLKENA inputs
allows two sequential 12-bit words to be presented synchronously
as a 24-bit on the B port. Data flow is controlled by the active-low
output enables (OEA, OEB). The control terminals are registered to
synchronize the bus direction changes with the CLK.
To ensure the high-impedance state during power up or power
down, OE should be tied to V
CC
through a pullup resistor, the
minimum value of the resistor is determined by the current-sinking
capability of the driver. Due to OE being routed through a register,
the active state of the outputs cannot be determined prior to the
arrival of the first clock pulse.
Active bus-hold circuitry is provided to hold unused or floating
data inputs at a valid logic level.
Logic Block Diagram
1
PS8171A
05/19/03
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74ALVCH16270
12-Bit To 24-Bit Registered Bus Exchanger
with 3-State Outputs
Product Pin Description
Pin Name
OE
CLK
SEL
CLKEN
A, 1B, 2B
GND
V
CC
Description
Output Enable Input (Active LOW)
Clock
Select (Active Low)
Clock Enable (Active Low)
3-State Outputs
Ground
Power
Truth Tables
(1)
Inputs
CLK
↑
↑
↑
↑
OEA
H
H
L
L
OEB
H
L
H
L
A
Z
Z
Active
Active
Outputs
1B, 2B
Z
Active
Z
Active
A to B Storage (OEB = L)
Product Pin Configuration
INPUTS
CLKENA1 CLKENA2 CLK
L
OEA
CLKEN1B
2B3
GND
2B2
2B1
VCC
A1
A2
A3
GND
A4
A5
A6
A7
A8
A9
GND
A10
A11
A12
VCC
1B1
1B2
GND
1B3
CLKEN2B
SEL
OUTPUTS
A
L
H
L
H
L
H
X
1B
L
(2)
H
(2)
L
(2 )
H
(2 )
1B0
(3 )
1B0
(3 )
1B0
(3 )
2B
2B0
(3 )
2B0
(3 )
L
H
L
H
2B0
(3 )
H
H
L
L
L
L
H
↑
↑
↑
↑
↑
↑
X
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
OEB
CLKENA2
2B4
GND
2B5
2B6
VCC
2B7
2B8
2B9
GND
2B10
2B11
2B12
1B12
1B11
1B10
GND
1B9
1B8
1B7
VCC
1B6
1B5
GND
1B4
CLKENA1
CLK
L
L
L
H
H
H
56-PIN
51
A56
50
V56
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
B to A Storage (OEA = L)
Inputs
CLKEN1B
H
X
L
L
X
X
CLKEN2B CLK
X
H
X
X
L
L
X
X
↑
↑
↑
↑
SEL
Η
L
Η
Η
L
L
1B
X
X
L
H
X
X
2B
X
X
X
X
L
H
Outputs
A
A0
( 3 )
A0
( 3 )
L
H
L
H
Notes:
1. H = High Signal Level
L = Low Signal Level
X = Irrelevant
Z = High Impedance
↑
= Transition, Low to High
2. Two CLK edges are needed to propagate data.
3. Output level before the indicated steady state
input conditions were established.
2
PS8171A
05/19/03
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74ALVCH16270
12-Bit To 24-Bit Registered Bus Exchanger
with 3-State Outputs
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ............................................................ –65°C to +150°C
Ambient Temperature with Power Applied ........................ –40°C to +85°C
Input Voltage Range, V
IN ......................................................
–0.5V to V
CC
+0.5V
Output Voltage Range, V
OUT ...............................................
–0.5V to V
CC
+0.5V
DC Input Voltage .................................................................... –0.5V to +5.0V
DC Output Current ............................................................................. 100mA
Power Dissipation .................................................................................. 1.0W
Note:
Stresses greater than those listed under MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
DC Electrical Characteristics
(Over the Operating Range, T
A
= –40°C to +85°C, V
CC
= 3.3V ± 10%)
Parame te rs
V
CC
V
IH(3)
V
IL(3)
V
IN(3)
V
OUT(3)
De s cription
Supply Voltage
Input HIGH Voltage
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
0
0
I
OH
= - 100
µ
A, V
CC
= Min. to Max.
Output
HIGH
Voltage
V
IH
= 1.7V, I
OH
= - 6mA, V
CC
= 2.3V
V
IH
= 1.7V, I
OH
= - 12mA, V
CC
= 2.3V
V
IH
= 2.0V, I
OH
= - 12mA, V
CC
= 2.7V
V
IH
= 2.0V, I
OH
= - 12mA, V
CC
= 3.0V
V
IH
= 2.0V, I
OH
= - 24mA, V
CC
= 3.0V
I
OL
= 100
µ
A, V
IL
= Min. to Max.
Output
LOW
Voltage
V
IL
= 0.7V, I
OL
= 6mA, V
CC
= 2.3V
V
IL
= 0.7V, I
OL
= 12mA, V
CC
= 2.3V
V
IL
= 0.8V, I
OL
= 12mA, V
CC
= 2.7V
V
IL
= 0.8V, I
OL
= 24mA, V
CC
= 3.0V
Output
HIGH
Current
V
CC
= 2.3V
V
CC
= 2.7V
V
CC
= 3.0V
Output
LOW
Current
V
CC
= 2.3V
V
CC
= 2.7V
V
CC
= 3.0V
3
Te s t Conditions
(1)
M in.
2.3
1.7
2.0
Typ.
(2)
M ax.
3.6
Units
Input LOW Voltage
Input Voltage
Output Voltage
0.7
0.8
V
CC
V
CC
V
CC
- 0.2
2.0
1.7
2.2
2.4
2.0
0.2
0.4
0.7
0.4
0.55
- 12
- 12
- 24
mA
12
12
24
PS8171A
05/19/03
V
V
OH
V
OL
I
OH(3)
I
OL(3)
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74ALVCH16270
12-Bit To 24-Bit Registered Bus Exchanger
with 3-State Outputs
DC Electrical Characteristics-Continued
(Over the Operating Range, T
A
= –40°C to +85°C, V
CC
= 3.3V ±10%)
Parame te rs De s cription
I
IN
Input Current
Te s t Conditions
(1)
V
IN
= V
CC
or GND, V
CC
= 3.6V
V
IN
= 0.7V, V
CC
= 2.3V
Input
Hold
Current
V
IN
= 1.7V, V
CC
= 2.3V
V
IN
= 0.8V, V
CC
= 3.0V
V
IN
= 2.0V, V
CC
= 3.0V
V
IN
= 0 to 3.6V, V
CC
= 3.6V
I
OZ
I
CC
∆I
CC
C
I
C
O
Output Current (3- STATE Outputs)
Supply Current
Supply Current per Input
@ TTL HIGH
Control Inputs
Outputs
V
OUT
= V
CC
or GND, V
CC
= 3.6V
V
CC
= 3.6V, I
OUT
= 0
µ
A,
V
IN
= GND or V
CC
V
CC
= 3.0V to 3.6V
One Input at V
CC
- 0.6V
Other Inputs at V
CC
or GND
V
IN
= V
CC
or GND, V
CC
= 3.3V
V
O
= V
CC
or GND, V
CC
= 3.3V
3.5
9
45
- 45
75
- 75
± 500
± 10
40
µA
M in.
Typ.
(2)
M a x.
±5
Units
I
IN
(
HOLD
)
750
pF
Notes:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 3.3V, +25°C ambient and maximum loading.
3. Unused Control Inputs must be held HIGH or LOW to prevent them from floating.
4
PS8171A
05/19/03
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74ALVCH16270
12-Bit To 24-Bit Registered Bus Exchanger
with 3-State Outputs
Timing Requirements over Operating Range
Parame te rs
f
CLOCK
t
W
Clock frequency
Pulse duration,
CLK HIGHor Low
A data before CLK
↑
B data before CLK
↑
t
SU
Setup time
CLKENA1 or CLKENA2
before CLK
↑
CLKEN1B or CLKEN2B
before CLK
↑
OE data before CLK
↑
A data after CLK
↑
B data after CLK
↑
t
H
Hold time
CLKENA1 or CLKENA2
before CLK
↑
CLKEN1B or CLKEN2B
before CLK
↑
OE after CLK
↑
∆
t/
∆V
(1)
Input Transition
Rise or Fall
De s cription
V
CC
= 2.5V ± 0.2V
M in.
0
3.3
4.1
0.9
3.5
3.4
4.4
0
1.4
0
0
0
0
10
M a x.
150
V
CC
= 2.7V
M in.
0
3.3
3.8
1.2
3.2
3
3.9
0
1
0.1
0
0
0
10
M a x.
150
V
CC
= 3.3V ± 0.3V
M in.
0
3.3
3.1
0.9
2.7
2.6
3.2
0.2
1.7
0.3
0.6
0.1
0
10
ns/V
ns
M a x.
150
Units
Mhz
Notes:
1. Unused control inputs must be held HIGH or LOW to prevent them from floating.
5
PS8171A
05/19/03
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