21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74ALVCT16260
12-Bit To 24-Bit Multiplexed D-Type Latch
with 3-STATE Outputs
Product Features
•
PI74ALVCT16260 is designed for low voltage operation
•
V
CC
= 2.3V to 3.6V
•
5V tolerant inputs and outputs
•
Hysteresis on all inputs
•
Typical V
OLP
(Output Ground Bounce)
< 0.8V at V
CC
= 3.3V, T
A
= 25°C
•
Typical V
OHV
(Output V
OH
Undershoot)
< 2.0V at V
CC
= 3.3V, T
A
= 25°C
•
Industrial operation at 40°C to +85°C
•
Packages available:
56-pin 240 mil wide plastic TSSOP (A)
56-pin 300 mil wide plastic SSOP (V)
Product Description
Pericom Semiconductor’s PI74ALVCT series of logic circuits are
produced in the Company’s advanced 0.5 micron CMOS technology,
achieving industry leading speed.
The PI74ALVCT16260 is a 12-bit to 24-bit multiplexed D-type latch
designed for 2.3V to 3.6 Vcc operation. It is used in applications
where two separate datapaths must be multiplexed onto, or
demultiplexed from, a single data path.
Typical applications include multiplexing and/or demulti-plexing
address and data information in microprocessor or bus-interface
applications. This device is also useful in memory-interleaving
applications.
Three 12-bit I/O ports (A1-A12, 1B1-1B12, and 2B1-2B12) are available
for address and/or data transfer. The output-enable (OE1B, OE2B,
and OEA) inputs control the bus transceiver functions. The OE1B
and OE2B control signals also allow bank control in the A-to-B
direction.
Address and/or data information can be stored using the internal
storage latches. The latch-enable (LE1B, LE2B, LEA1B, and LEA2B)
inputs are used to control data storage. When the latch-enable input
is HIGH, the latch is transparent. When the latch-enable input goes
LOW, the data present at the inputs is latched and remains latched
until the latch-enable input is returned HIGH.
Logic Block Diagram
LE1B
LE2B
LEA1B
LEA2B
OE2B
2
27
30
55
56
To ensure the high-impedance state during power up or power down,
OE should be tied to Vcc through a pullup resistor, the minimum value
of the resistor is determined by the current-sinking capability of the
driver.
The ALVCT16260 can be driven from either 3.3V or 5V devices
allowing it to be used in mixed 3V/5V systems.
29
OE1B
1
28
G1
A1
8
1
1
C1
23
1D
1
B
1
OEA
SEL
C1
6
1D
2
B
1
C1
1D
C1
1D
TO 11 OTHER CHANNELS
1
PS8131A 03/17/98
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74ALVCT16260
12-Bit To 24-Bit Multiplexed D-Type Latch with 3-State Outputs
Truth Tables
(1)
B to A (OEB = H)
Inputs
1B
2B
SEL
LE1B
LE2B
OEA
Output
A
Product Pin Description
Pin Name
OE
SEL
LE
A,1B,2B
A,1B,2B
GND
V
CC
Description
Output Enable Input (Active LOW)
Select
Latch Enable
Data Inputs
3-State Outputs
Ground
Power
H
L
X
X
X
X
X
H
L
X
X
H
H
H
L
L
L
X
H
H
L
X
X
X
X
X
X
X
H
H
L
X
L
L
L
L
L
L
H
H
L
A
0
H
L
A
0
Z
Product Pin Configuration
X
X
OE2B
LEA2B
2B4
GND
2B5
2B6
VCC
2B7
2B8
2B9
GND
2B10
2B11
2B12
1B12
1B11
1B10
GND
1B9
1B8
1B7
VCC
1B6
1B5
GND
1B4
LEA1B
OE1B
OEA
LE1B
2B3
GND
2B2
2B1
VCC
A1
A2
A3
GND
A4
A5
A6
A7
A8
A9
GND
A10
A11
A12
VCC
1B1
1B2
GND
1B3
LE2B
SEL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
X
A to B (OEA = H)
56-PIN
51
V56
50
A56
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
Inputs
A
H
L
H
L
H
L
X
X
X
X
X
Note:
1. H =
L =
X =
Z =
Outputs
1B
H
L
H
L
1B0
1B0
1B0
Z
Active
Z
Active
2B
H
L
2B0
2B0
H
L
2B0
Z
Z
Active
Active
LEA1B LEA2B OE1B OE2B
H
H
H
H
L
L
L
X
X
X
X
H
H
L
L
H
H
L
X
X
X
X
L
L
L
L
L
L
L
H
L
H
L
L
L
L
L
L
L
L
H
H
L
L
High Signal Level
Low Signal Level
Irrelevant
High Impedance
2
PS8131A
03/17/98
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74ALVCT16260
12-Bit To 24-Bit Multiplexed D-Type Latch with 3-State Outputs
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ........................................................... 65°C to +150°C
Ambient Temperature with Power Applied ........................ 40°C to +85°C
Input Voltage Range, V
IN ......................................................
0.5V to V
CC
+0.5V
Output Voltage Range, V
OUT ...............................................
0.5V to V
CC
+0.5V
DC Input Voltage .................................................................... 0.5V to +5.0V
DC Output Current ............................................................................ 100 mA
Power Dissipation .................................................................................. 1.0W
Note:
Stresses greater than those listed under MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
DC Electrical Characteristics
(Over the Operating Range, T
A
= 40°C to +85°C, V
CC
= 3.3V ± 10%)
Parame te rs
V
CC
V
IH(3)
V
IL(3)
V
IN(3)
V
OUT(3)
D e s cription
Supply Voltage
Input HIGH Voltage
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
0
0
I
OH
= - 100
m
A, V
CC
= Min. to Max.
O utput
HIGH
Voltage
V
IH
= 1.7V, I
OH
= - 6mA, V
CC
= 2.3V
V
IH
= 1.7V, I
OH
= - 12mA, V
CC
= 2.3V
V
IH
= 2.0V, I
OH
= - 12mA, V
CC
= 2.7V
V
IH
= 2.0V, I
OH
= - 12mA, V
CC
= 3.0V
V
IH
= 2.0V, I
OH
= - 24mA, V
CC
= 3.0V
I
OL
= 100
m
A, V
IL
= Min. to Max.
V
OL
O utput
LO W
Voltage
V
IL
= 0.7V, I
OL
= 6mA, V
CC
= 2.3V
V
IL
= 0.7V, I
OL
= 12mA, V
CC
= 2.3V
V
IL
= 0.8V, I
OL
= 12mA, V
CC
= 2.7V
V
IL
= 0.8V, I
OL
= 24mA, V
CC
= 3.0V
I
OH(3)
O utput
HIGH
Current
V
CC
= 2.3V
V
CC
= 2.7V
V
CC
= 3.0V
V
CC
= 2.3V
V
CC
= 2.7V
V
CC
= 3.0V
V
CC
- 0.2
2.0
1.7
2.2
2.4
2.0
0.2
0.4
0.7
0.4
0.55
- 12
- 12
- 24
12
12
24
mA
V
Te s t Conditions
(1)
M in.
2.3
1.7
2.0
Typ.
(2)
M ax.
3.6
5.5
5.5
0.7
0.8
5.5
5.5
Units
Input LO W Voltage
Input Voltage
O utput Voltage
V
OH
I
OL(3)
O utput
LO W
Current
3
PS8131A 03/17/98
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74ALVCT16260
12-Bit To 24-Bit Multiplexed D-Type Latch with 3-State Outputs
DC Electrical Characteristics-
Continued
(Over the Operating Range, T
A
= 40°C to +85°C, V
CC
= 3.3V ± 10%)
Parame te rs De s cription
I
IN
I
OZ
I
CC
DI
CC
C
I
C
IO
Input Current
Output Current (3- STATE Outputs)
Supply Current
Supply Current per Input
@ TTL HIGH
Control Inputs
Outputs
Te s t Conditions
(1)
V
IN
= V
CC
or GND, V
CC
= 3.6V
V
OUT
= 5.5V or GND
V
CC
= 3.6V, I
OUT
= 0
m
A,
V
IN
= GND or V
CC
V
CC
= 3.0V to 3.6V
One Input at V
CC
- 0.6V
Other Inputs at V
CC
or GND
V
IN
= V
CC
or GND, V
CC
= 3.3V
V
O
= V
CC
or GND, V
CC
= 3.3V
3.5
9
M in.
Typ.
(2)
M ax.
5
±10
40
750
mA
Units
pF
Notes:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 3.3V, +25°C ambient and maximum loading.
3. Unused Control Inputs must be held HIGH or LOW to prevent them from floating.
Timing Requirements over Operating Range
Parame te rs
t
W
t
SU
t
H
D
t/
Dv
(1)
De s cription
Pulse duration, LE1B, LE2B, LEA1B,
or LEA2B HIGH
Setup time data before LE1B, LE2B,
LEA1B, or LEA2B
Hold time data after LE1B, LE2B,
LEA1B, or LEA2B
Input Transition Rise or Fall
V
CC
= 2.5V ± 0.2V
M in.
3.3
1.4
1.6
0
10
M ax.
V
CC
= 2.7V
M in.
3.3
1.1
1.9
0
10
M ax.
V
CC
= 3.3V ± 0.3V
M in.
3.3
1.1
1.5
0
10
ns/v
ns
M ax.
Units
Note:
1. Unused control inputs must be held HIGH or LOW to prevent them from floating.
4
PS8131A
03/17/98
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74ALVCT16260
12-Bit To 24-Bit Multiplexed D-Type Latch with 3-State Outputs
Switching Characteristics Over Operating Range
(1)
Parame te rs
V
CC
= 2.7V
V
CC
= 2.5V ± 0.2V
From
To
(INPUT) (OUTPUT) M in.
(2)
M ax.
M in.
(
2)
M ax.
A or B
t
PD
t
EN
t
DIS
LE
SEL
OE
OE
B or A
A or B
A
A or B
1.2
1.0
1.2
1.0
1.7
6.0
6.2
7.5
7.2
5.9
5.1
5.2
6.6
6.4
5.0
V
CC
= 3.3V ± 0.3V
M in.
(2)
1.2
1.0
1.1
1.0
1.3
M ax.
4.9
5.0
5.6
5.4
4.6
ns
Units
Notes:
1. See test circuit and wave forms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
Operating Characteristics, T
A
= 25ºC
Parame te r
C
PD
Power Dissipation
Capacitance
O utputs Enabled
O utputs Disabled
Te s t Conditions
C
L
= 50pF,
f = 10 MHz
V
CC
= 2.5V ± 0.2V
87
80.5
V
CC
= 3.3V ± 0.3V
120
118
Typical
Units
pF
5
PS8131A 03/17/98
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