ADVANCE INFORMATION
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
1
2109876543212109876543210987654321098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74ALVTC16260
2.5V 12-Bit to 24-Bit Multiplexed
D-Type Latch with 3-State Outputs
Product Features
PI74ALVTC16260 is designed for low voltage operation,
V
DD
= 1.65V to 3.6V
Supports Live Insertion
3.6V I/O Tolerant Inputs and Outputs
Bus Hold
High Drive, 32/64mA @ 3.3V
Uses patented noise reduction circuitry
Power-off high impedance inputs and outputs
Industrial operation at 40°C to +85°C
Packages available:
56-pin 240-mil wide plastic TSSOP (A56)
56-pin 173-mil wide plastic TVSOP (K56)
Product Description
Pericom Semiconductors PI74ALVTC series of logic circuits are
produced using the Companys advanced 0.35 micron CMOS
technology, achieving industry leading speed.
The PI74ALVTC16260 is a 12-bit to 24-bit multiplexed D-type latch
designed for 1.65V to 3.6 V
DD
operation. It is used in applications
where two separate datapaths must be multiplexed onto, or
demultiplexed from, a single data path.
Typical applications include multiplexing and/or demulti-plexing
address and data information in microprocessor or bus-interface
applications. This device is also useful in memory-interleaving
applications.
Three 12-bit I/O ports (A1-A12, 1B1-1B12, and 2B1-2B12) are
available for address and/or data transfer. The output-enable
(OE1B, OE2B, and OEA) inputs control the bus transceiver functions.
The OE1B and OE2B control signals also allow bank control in the
A-to-B direction.
Address and/or data information can be stored using the internal
storage latches. The latch-enable (LE1B, LE2B, LEA1B, and LEA2B)
inputs are used to control data storage. When the latch-enable input
is HIGH, the latch is transparent. When the latch-enable input goes
LOW, the data present at the inputs is latched and remains latched
until the latch-enable input is returned HIGH.
To ensure the high-impedance state during power up or power
down, OE should be tied to V
DD
through a pullup resistor, the
minimum value of the resistor is determined by the current-sinking
capability of the driver.
G1
C1
1
1
23
1D
1
B
1
Logic Block Diagram
LE1B
LE2B
LEA1B
LEA2B
OE2B
2
27
30
55
56
29
OE1B
1
28
OEA
SEL
A1
8
The family offers both I/O Tolerant, which allows it to operate in
mixed 1.65/3.6V systems, and Bus Hold, which retains the data
inputs last state preventing floating inputs and eliminating the
need for pullup/down resistors.
C1
6
1D
2
B
1
C1
1D
C1
1D
TO 11 OTHER CHANNELS
1
PXXXX
04/11/00
ADVANCE INFORMATION
321098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74ALVTC16260
2.5V 12-Bit To 24-Bit Multiplexed
D-Type Latch with 3-State Outputs
Product Pin Description
Pin Name
OE
SEL
LE
A,1B,2B
A,1B,2B
GND
V
DD
Description
Output Enable Input (Active LOW)
Select
Latch Enable
Data Inputs
3-State Outputs
Ground
Power
Truth Tables
(1)
B to A (OEB = H)
Inputs
1B
H
L
X
X
X
X
X
2B
X
X
X
H
L
X
X
SEL LE1B LE2B OEA
H
H
X
L
H
H
X
L
H
L
X
L
L
X
H
L
L
X
H
L
L
X
L
L
X
X
X
H
A to B (OEA = H)
INPUTS
A
H
L
H
L
H
L
X
X
X
X
X
LEA1B
H
H
H
H
L
L
L
X
X
X
X
LEA2B
H
H
L
L
H
H
L
X
X
X
X
O E1B
L
L
L
L
L
L
L
H
L
H
L
O E2B
L
L
L
L
L
L
L
H
H
L
L
Output
A
H
L
A
0
H
L
A
0
Z
Product Pin Configuration
OEA
LE1B
2B3
GND
2B2
2B1
VDD
A1
A2
A3
GND
A4
A5
A6
A7
A8
A9
GND
A10
A11
A12
VDD
1B1
1B2
GND
1B3
LE2B
SEL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
56-Pin
46
A, K
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
OE2B
LEA2B
2B4
GND
2B5
2B6
VDD
2B7
2B8
2B9
GND
2B10
2B11
2B12
1B12
1B11
1B10
GND
1B9
1B8
1B7
VDD
1B6
1B5
GND
1B4
LEA1B
OE1B
OUTPUTS
1B
H
L
H
L
1B0
1B0
1B0
Z
Active
Z
Active
2B
H
L
2B0
2B0
H
L
2B0
Z
Z
Active
Active
Note:
1. H = High Signal Level
L = Low Signal Level
X = Irrelevant
Z = High Impedance
2
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04/11/00
ADVANCE INFORMATION
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74ALVTC16260
2.5V 12-Bit To 24-Bit Multiplexed
D-Type Latch with 3-State Outputs
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Supply Voltage Range, V
DD ........................................................
0.5V to 4.6V
Input Voltage Range, V
I ................................................................
0.5V to 4.6V
Output Voltage Range, V
O
(3-Stated) .............................. 0.5V to 4.6V
Output Voltage Range, V
O(1)
(Active) .................. 0.5V to V
DD
+0.5V
DC Input Diode Current (I
IK
) V
I
< 0V ........................................ 50mA
DC Output Diode Current (I
OK
)
V
O
< 0V ................................................................................... 50mA
V
O
> V
DD ....................................................................................................
±50mA
DC Output Source/Sink Current (I
OH
/I
OL
) ........................... 4/128mA
DC V
DD
or GND Current per Supply Pin (I
CC
or GND) ............ ±100mA
Storage Temperature Range, T
stg
.................................. 65°C to150°C
Note:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the device. This
is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the
operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
Recommended Operating Conditions
(2)
M in.
V
DD
V
IH
V
IL
V
I
V
O
Supply voltage
High- level input voltage
Low- level input voltage
Input voltage
Output voltage
Active State
Off State
V
DD
=
V
DD
=
V
DD
=
V
DD
=
3.0V to 3.6V
3.0V to 3.6V
2.3V to 2.7V
1.65V to 1.95V
0
−
40
Operating
Data Retention Only
V
DD
= 2.7V to 3.6V
V
DD
= 2.7V to 3.6V
0.3
0
0
1.65
1.2
2.0
0.8
3.6
V
DD
3.6
32/64
±24
±18
±6
10
85
mA
ns/V
C
V
M ax.
3.6
3.6
Units
Output current in I
OH
/I
OL
∆
t/
∆v
T
A
Input transistion rise or fall rate
(3)
Operating free- air temperature
Notes:
1. Absolute maximum of I
O
must be observed.
2. Unused control inputs must be held HIGH or LOW to prevent them from floating.
3 As measured between 0.8V and 2.0V, V
DD
= 3.0V.
3
PXXXX
04/11/00
ADVANCE INFORMATION
321098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74ALVTC16260
2.5V 12-Bit To 24-Bit Multiplexed
D-Type Latch with 3-State Outputs
(unless otherwise noted)
Electrical Characteristics over Recommended Operating Free-Air Temperature Range
DC Characteristics (2.7V<V
DD
≤
3.6V)
Parame te r
V
IK
Input Clamp Diode
Conditions
I
IK
=
−
18mA
I
O H
=
−
100
µA
I
O H
=
−
12mA
V
O H
HIGH Level Output Voltage
I
O H
=
−
18mA
I
O H
=
−
24mA
I
O H
=
−
32mA
I
O L
= 100
µA
I
O L
= 12mA
V
O L
LOW Level Output Voltage
I
O L
= 18mA
I
O L
= 24mA
I
O L
= 32mA
I
O L
= 64mA
I
I
I
O Z
I
O FF
I
HO LD
Input Leakage Current
3- State Output Leakage
Power- OFF Leakage Current
Bus Hold Current
A or B Outputs
V
I
= V
DD
, or GND
V
O
= 3.6V
V
I
or V
O
≤
3.6V
V
I
= 0.8V
V
I
= 2.0V
V
I
= 0 to 3.6V
I
DD
∆I
DD
Quiescent Supply Current
Increase in I
DD
per input
V
I
= V
DD
or GND
V
DD
≤
(V
I
,V
O
)
≤
3.6V
V
IH
= V
DD
0.6V,
Other inputs at V
DD
or Gnd
2.7 - 3.6
3.6
2.7
0
3.0
3.6
75
75
±500
50
±50
400
µA
3.0
2.7 - 3.6
2.7
3.0
V
D D
3.0
2.7 - 3.6
2.7
V
DD
0.2
2.2
2.4
2.2
2.0
0.2
0.4
0.4
0.45
0.5
0.55
±5.0
±10
10
V
M in.
Typ.
M ax.
1.2
Units
4
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04/11/00
ADVANCE INFORMATION
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74ALVTC16260
2.5V 12-Bit To 24-Bit Multiplexed
D-Type Latch with 3-State Outputs
Electrical Characteristics over Recommended Operating Free-Air Temperature Range
(unless otherwise noted; continued from previous page)
DC Characteristics (2.3V
≤
V
DD
≤
2.7V)
De s cription
V
IK
V
OH
Parame te rs
Input Clamp Diode
Conditions
I
IK
= 18mA
I
OH
= 100
µA
I
OH
= 12mA
I
OH
= 18mA
I
OL
= 100
µA
I
OL
= 12mA
I
OL
= 18mA
I
OL
= 24mA
V
I
= V
DD
or GND
V
O
= 3.6
V
V
I
or V
O
≤ 3.6
V
V
I
= 0.7V
V
I
= 1.7V
V
I
= V
DD
or GND
V
DD
≤
(V
I
,V
O
)
≤
3.6V
V
IH
= V
DD
0.6V,
Inputs at V
DD
or Gnd
V
DD
2.3
2.3 - 2.7
2.3
2.3 - 2.7
M in.
Typ.
M ax.
1.2
Units
V
DD
0.2
1.8
1.7
0.2
0.4
V
HIGH Level Output Voltage
V
OL
LOW Level Output Voltage
2.3
0.5
0.55
I
I
I
OZ
I
OFF
I
HOLD(1)
I
DD
∆Ι
DD
Input Leakage Current
3- State Output Leakage
Power- OFF Leakage Current
Bus Hold Current
A or B Outputs
Quiescent Supply Current
Increase in I
DD
per input
2.7
2.3
0
2.5
90
90
±5.0
±10
10
µA
40
2.3 - 2.7
±40
400
µA
Note:
1. Not Guaranteed
5
PXXXX
04/11/00
Embedded System
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