21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74AVC+16652
2.5V 16-Bit Bus Transceiver and
Register with 3-State Outputs
Product Features
PI74AVC
+
16652 is designed for low-voltage operation,
V
CC
= 1.65V to 3.6V
True ±24mA Balanced Drive @ 3.3V
I
OFF
supports partial power-down operation
3.6V I/O Tolerant Inputs and Outputs
All outputs contain a patented DDC
(Dynamic DriveControl) circuit that reduces noise without
degrading propagation delay.
Industrial operation: 40°C to +85°C
Available Packages:
56-pin 240 mil wide plastic TSSOP (A)
56-pin 173 mil wide plastic TVSOP (K)
Product Description
Pericom Semiconductors PI74AVC+ series of logic circuits are
produced using the Companys advanced submicron CMOS
technology, achieving industry leading speed.
The PI74AVC+16652 is a 16-bit bus transceiver and register
designed for low 1.65V to 3.6V V
CC
operation. It consists of D-type
flip-flops and control circuitry arranged for multiplexed transmission
of data directly from the data bus or from the internal storage
registers. The device can be used as two 8-bit transceivers or one
16-bit transceiver.
Complementary Output Enable (OEAB and OEBA) inputs are
provided to control the transceiver functions. Select Control (SAB
and SBA) inputs are provided to select whether real-time or stored
data is transferred. A low input level selects real-time data, and a high
input level selects stored data. Circuitry used for Select Control
eliminates the typical decoding glitch that occurs in a multiplexer
during the transition between stored and real-time data.
Data on the A or B bus, or both, can be stored in the internal D flip-
flops by low-to-high transitions at the appropriate clock (CLKAB
or CLKBA) inputs regardless of the levels on the Select Control or
Output Enable inputs. When SAB and SBA are in the real-time
transfer mode, it also is possible to store data without using the
internal D-type flip-lops by simultaneously enabling OEAB and
OEBA. In this configuration, each output reinforces its input. Thus,
when all other data sources to the two sets of bus lines are in the
high-impedance state, each set of bus lines remains at its last level
configuration.
To ensure the high-impedance state during power up or power
down, OEBA should be tied to V
CC
through a pull-up resistor and
OEAB should be tied to GND through a pull-down resistor; the
minimum value of the resistor is determined by the current-sinking
current sourcing capability of the driver.
Logic Block Diagram
1OEBA
56
1OEAB
1
1CLKBA
1SBA
1CLKAB
1SAB
55
54
2
3
One of Eight Channels
1D
C1
1A1
5
52
1B1
1D
C1
TO SEVEN OTHER CHANNELS
2OEBA
29
2OEAB
28
2CLKBA
2SBA
2CLKAB
2SAB
30
31
27
26
One of Eight Channels
1D
C1
2A1
15
42
2B1
1D
C1
TO SEVEN OTHER CHANNELS
1
PS8550
07/31/01
321098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
321098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74AVC+16652
2.5V 16-Bit Bus Transceiver and
Register with 3-State Outputs
Product Pin Description
Pin Name
O EAB
O EBA
xCLK AB,
xCLK BA
xSAB, xSBA
xAx
xBx
GND
V
CC
D e s cription
O utput Enable Inputs (Active HIGH)
O utput Enable Inputs (Active LO W)
Clock Pulse Inputs
Select Control Inputs
Data Register A Inputs,
Data Register B O utputs
Data Register B Inputs,
Data Register A O utputs
Ground
Power
Pin Configuration
1
OEAB
1
CLKAB
1
SAB
GND
1
A
1
1
A
2
V
CC
1
A
3
1
A
4
1
A
5
GND
1
A
6
1
A
7
1
A
8
2
A
1
2
A
2
2
A
3
GND
2
A
4
2
A
5
2
A
6
V
CC
2
A
7
2
A
8
GND
2
SAB
2
CLKAB
2
OEAB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56-Pin
A, K
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
OEBA
1
CLKBA
1
SBA
GND
1
B
1
1
B
2
V
CC
1
B
3
1
B
4
1
B
5
GND
1
B
6
1
B
7
1
B
8
2
B
1
2
B
2
2
B
3
GND
2
B
4
2
B
5
2
B
6
V
CC
2
B
7
2
B
8
GND
2
SBA
2
CLKBA
2
OEBA
Truth Table
(1)
Inputs
OEAB
L
L
X
H
L
L
L
L
H
H
H
OEBA
H
H
H
H
X
L
L
L
H
H
L
CLKAB
H or L
H or L
X
X
X
H or L
H or L
CLKBA
H or L
H or L
X
H or L
X
X
H or L
SAB
X
X
X
X* *
X
X
X
X
L
H
H
SB A
X
X
X
X
X
X* *
L
H
X
X
H
Input
Input
Input
Input
Unspecified* *
Output
Output
Output
Input
Input
Output
Data I/O*
A1 - A8
B1 - B8
Input
Input
Unspecified* *
Output
Input
Input
Input
Input
Output
Output
Output
Ope ration or Function
Isolation
Store A and B data
Store A, hold B
Store A in both registers
Hold A, store B
Store B in both registers
Real- time B data to A bus
Stored B data to A bus
Real- time A data to B bus
Stored A data to B bus
Stored A data to B bus and
stored B data to A bus
Notes:
1. H = High Voltage Level, X = Dont Care, L = Low Voltage Level,
↑
= LOW-to-HIGH Transition
* The data output functions may be enabled or disabled by a variety of level combinations at the OEAB or OEBA inputs. Data input
functions are always enabled, i.e., data at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs.
** Select control = L; clocks can occur simultaneously. Select control = H; to load both registers, clocks must be staggered.
2
PS8550
07/31/01
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74AVC+16652
2.5V 16-Bit Bus Transceiver and
Register with 3-State Outputs
REAL-TIME TRANSFER
BUS B to A
REAL-TIME TRANSFER
BUS A to B
BUS
A
BUS
B
BUS
A
BUS
B
OEAB OEBA
L
L
xCLKAB
X
xCLKBA
X
xSAB
X
xSBA
L
OEAB OEBA xCLKAB
H
H
X
xCLKBA
X
xSAB
L
xSBA
X
STORAGE FROM
A,B, or A and B
TRANSFER STORED
DATA to A and/or B
BUS
A
BUS
B
BUS
A
BUS
B
OEAB OEBA xCLKAB
X
H
↑
L
X
X
↑
L
H
xCLKBA
X
↑
↑
xSAB
X
X
X
xSBA
X
X
X
OEAB OEBA xCLKAB
H
L
H or L
xCLKBA
H or L
xSAB
H
xSBA
H
Note:
1. Cannot transfer data to A bus and B bus simultaneously.
3
PS8550
07/31/01
321098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
321098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74AVC+16652
2.5V 16-Bit Bus Transceiver and
Register with 3-State Outputs
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Supply voltage range, V
CC ..................................................
0.5V to +4.6V
Input voltage range, V
I ..........................................................
0.5V to +4.6V
Voltage range applied to any output in the
high-impedance or power-off state, V
O(1) ..............
0.5V to +4.6V
Voltage range applied to any output in the
high or low state, V
O(1,2) ..........................................
0.5V to V
CC
+0.5V
Input clamp current, I
IK
(V
I
<0) ............................................ 50mA
Output clamp current, I
OK
(V
O
<0) ...................................... 50mA
Continuous output current, I
O ............................................................
±50mA
Continuous current through each V
CC
or GND ................. ±100mA
Package thermal impedance, q
JA(3)
: package A .................. 64°C/W
package K ................... 48°C/W
Storage Temperature range, T
stg .....................................
65°C to 150°C
Note:
Stresses greater than those listed under MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
Notes:
1. Input & output negative-voltage ratings may be exceeded if the
input and output curent rating are observed.
2. Output positive-voltage rating may be exceeded up to 4.6V
maximum if theoutput current rating is observed.
3. package thermal impedance is calculated in accordance with
JESD 51.
Recommended Operating Conditions
(1)
M in.
V
CC
V
IH
Supply Voltage
High- level Input Voltage
Operating
Data retention only
V
CC
= 1.2V
V
CC
= 1.65V to 1.95V
V
CC
= 2.3V to 2.7V
V
CC
= 3V to 3.6V
V
IL
Low- level Input Voltage
V
CC
= 1.2V
V
CC
= 1.65V to 1.95V
V
CC
= 2.3V to 2.7V
V
CC
= 3V to 3.6V
V
I
V
O
Input Voltage
Output Voltage
Active State
3- State
I
OH
High- level output current
V
CC
= 1.65V to 1.95V
V
CC
= 2.3V to 2.7V
V
CC
= 3V to 3.6V
I
OL
Low- level output current
V
CC
= 1.65V to 1.95V
V
CC
= 2.3V to 2.7V
V
CC
= 3V to 3.6V
∆t∆
v Input transition rise or fall rate
T
A
Operating free- air temperature
V
CC
= 1.65V to 3.6V
40
0
0
0
1.65
1.2
V
CC
0.65 x V
CC
1.7
2
Gnd
0.35 x V
CC
0.7
0.8
3.6
V
CC
3.6
6
12
24
6
12
24
5
85
ns/V
°C
mA
M ax.
3.6
Units
V
Note:
1. All unused inputs must be held at V
CC
or GND to ensure proper device operation.
4
PS8550
07/31/01
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74AVC+16652
2.5V 16-Bit Bus Transceiver and
Register with 3-State Outputs
DC Electrical Characteristics
(Over Operating Range, T
A
= 40°C +85°C)
Parame te rs
I
OH
= 100µA
I
OH
= 6mA
V
OH
I
OH
= 12mA
I
OH
= 24mA
I
OL
= 100µA
V
OL
I
OL
= 6mA
I
OL
= 12mA
I
OL
= 24mA
I
I
Control Inputs
I
OFF
I
OZ
I
CC
Control Inputs
C
I
Data Inputs
C
O
Outputs
V
O
= V
CC
or GND
V
I
= V
CC
or GND
V
I
= V
CC
or GND
V
I
or V
O
= 3.6V
V
I
= V
CC
or GND
V
O
= V
CC
or GND
I
O
= 0
V
IH
= 0.57V
V
IH
= 0.7V
V
IH
= 0.8V
V
IH
= 1.07V
V
IH
= 1.7V
V
IH
= 2V
Te s t Conditions
(1
)
V
CC
1.65V to 3.6V
1.65V
2.3V
3V
1.65V to 3.6V
1.65V
2.3V
3V
3.6V
0
3.6V
3.6V
2.5V
3.3V
2.5V
3.3V
2.5V
3.3V
M in.
V
CC
0.2V
1.2
1.75
2.0
V
0.2
0.45
0.55
0.8
±2.5
±10
±10
40
4
4
6
6
8
8
pF
µA
M ax.
Units
Note:
1. Typical values are measured at T
A
= 25°C.
5
PS8550
07/31/01
京公网安备 11010802033920号
EEWORLD
