21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74AVC16834
18-Bit Universal Bus Driver
with 3-State Outputs
Product Features
• Very high-speed, low-noise universal bus driver with
embedded resistor outputs
• Meets PC133 SDRAM Registered DIMM specification
• Implements output impedance control for low-noise and
heavy-load applications
• Fast Propagation Delay:
2.5ns max. for 50pF test load
• V
CC
= 3.3V or 2.5V or 1.8V
• Packaging (Pb-free & Green available):
– 56-pin 240 mil wide plastic TSSOP (A)
Product Description
The 18-bit PI74AVC16834 universal bus driver is designed for 1.8V
to 3.6V V
CC
operation.
Data flow from A to Y is controlled by Output Enable (OE). The device
operates in the transparent mode when LE is LOW. The A data is
latched if CLK is held at a high or low logic level. If LE is HIGH, the
A-bus is stored in the latch/flip-flop on the low-to-high transition of
CLK. When OE is HIGH, the outputs are in the high-impedance state.
The PI74AVC16834 bus driver is designed to drive an array of
133 MHz synchronous memory chips, with minimal undershoot/
overshoot noise, and to meet the input signal rise/fall time
requirement of memory chips.
The output drivers of this part have an embedded series-resistor.
For DIMM module design, no external series termination resistors
near the buffer drivers or any other termination resistors are
required. This feature simplifies DIMM module layout design, and
results in cost savings.
Product Pin Configuration
NC
NC
Y1
GND
Y2
Y3
V
CC
Y4
Y5
Y6
GND
Y7
Y8
Y9
Y10
Y11
Y12
GND
Y13
Y14
Y15
V
CC
Y16
Y17
GND
Y18
OE
LE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
GND
NC
A1
GND
A2
A3
V
CC
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
V
CC
A16
A17
GND
A18
CLK
GND
09-0003
1
PS8375H 10/27/09
Product Pin Description
Pin Name
OE
LE
CLK
A
Y
GND
V
CC
Description
Output Enable Input (Active LOW)
Latch Enable (Active LOW)
Clock Input
Data Input
Data Output
Ground
Power
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74AVC16834
18-Bit Universal Bus Driver
with 3-State Outputs
Logic Block Diagram
27
30
28
Truth Table
(1)
Inputs
OE
CLK
OE
H
L
L
LE
X
L
L
H
H
H
H
CLK
X
X
X
↑
↑
H
L
A
X
L
H
L
H
X
X
Outputs Y
Z
L
H
L
H
Yo
(2)
Yo
(3)
LE
L
L
A1
54
1D
C1
CLK
3
Y1
L
L
TO 17 OTHER CHANNELS
Notes:
1 H = High Signal Level
L = Low Signal Level
Z = High Impedance
↑
= Transition LOW-to-HIGH
X = Irrelevant
2. Output level before the indicated steady-state input
conditions were established, provided that CLK is HIGH
before LE goes HIGH.
3. Output level before the indicated steady-state input
conditions were established.
09-0003
2
PS8376G 10/27/09
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74AVC16834
18-Bit Universal Bus Driver
with 3-State Outputs
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ............................................................................................................. –65°C to +150°C
Ambient Temperature with Power Applied .............................................................................. –40°C to +85°C
Supply Voltage Range, V
CC ....................................................................................................................................................................................
–0.5V to +4.6V
Input Voltage Range, V
I(1) .......................................................................................................................................................................................
–0.5V to +4.6V
Voltage range applied to any output in the high-impedance or power-off state, V
O(1)
..............–0.5V to +4.6V
Voltage range applied to any output in the high or low state, V
O(1,2)
.................................. –0.5V to V
CC
+0.5V
Input clamp current, I
IK
(V
I
<0) ............................................................................................................... –50mA
Output clamp current, I
OK
(V
O
<0) ...........................................................................................................–50mA
Continuous output current, I
O
................................................................................................................ ±50mA
Continuous current through each V
CC
or GND ..................................................................................... ±100mA
Package thermal impedance,
θ
JA(3)
: A (TSSOP) package ..................................................................... 81°C/W
Notes:
Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
1. Input and output negative voltage ratings may be exceeded if the input and output current ratings are observed.
2. Output positive voltage rating may be exceeded up to 4.6V maximum if the output current rating is observed.
3. Package thermal impedance is calculated in accordance with JESD 51.
09-0003
3
PS8376G 10/27/09
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74AVC16834
18-Bit Universal Bus Driver
with 3-State Outputs
Recommended Operating Conditions
(1)
Parame te rs
V
CC
De s cription
Supply Voltage
Data Retention Only
V
CC
= 1.2V
V
CC
= 1.65V to 1.95V
V
IH
High- level Input Voltage
V
CC
= 2.3V to 2.7V
V
CC
= 3V to 3.6V
V
CC
= 1.2V
V
CC
= 1.65V to 1.95V
V
IL
Low- level Input Voltage
V
CC
= 2.3V to 2.7V
V
CC
= 3V to 3.6V
V
IN
V
OUT
Input Voltage
Active State
Output Voltage
3- State
V
CC
= 1.65V to 1.95V
I
OHS
High- level Output Current
(2)
V
CC
= 2.3V to 2.7V
V
CC
= 3V to 3.6V
V
CC
= 1.65V to 1.95V
I
OLS
Low- level Output Current
(2)
V
CC
= 2.3V to 2.7V
V
CC
= 3V to 3.6V
Δ
t/
Δv
T
A
Input transition rise or fall rate
Operating Free- Air Temperature
V
CC
= 1.65V to 3.6V
–4 0
0
3.6
–4
–8
–12
mA
4
8
12
5
85
ns/V
°C
0
0
0.7
0.8
3.6
V
CC
1.7
2
GND
0.35 x V
CC
V
1.2
V
CC
0.65 x V
CC
Te s t Conditions
Operating
M in.
1.65
M a x.
3. 6
Units
Notes:
1. Unused control inputs must be held HIGH or LOW to prevent them from floating.
2. Dynamic drive is greater than standard output drive of I
OH
= –24mA and I
OL
= 24mA
09-0003
4
PS8376G 10/27/09
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74AVC16834
18-Bit Universal Bus Driver
with 3-State Outputs
DC Electrical Characteristics
(Over the Operating Range, T
A
= –40°C to +85°C, V
CC
= 3.3V ± 10%)
Parame te rs
I
OHS
= –100
μA
V
OH
I
OHS
= –4mA
I
OHS
= –8mA
I
OHS
= –12mA
I
OLS
= 100
μA
V
OL
I
OLS
= 4mA
I
OLS
= 8mA
I
OLS
= 12mA
I
I
I
OFF
I
OZ(3)
I
CC
Control Inputs
3.3
C
I
Data Input
3.3
2.5
C
O
Outputs
V
O
= V
CC
or GND
3.3
4.0
6. 5
6. 5
V
I
= V
CC
or GND
2.5
4.5
4.0
pF
Control Inputs
V
I
= V
CC
or GND
V
I
= 0 or 3.6V
V
O
= V
CC
or GND
V
I
= V
CC
or GND
OE = V
CC
I
O
= 0
Te s t Conditions
V
IH
or V
IL
V
IH
= 1.07V
V
IH
= 1.7V
V
IH
= 2V
V
IH
or V
IL
V
IL
= 0.57V
V
IL
= 0.7V
V
IL
= 0.8V
V
CC
(1)
1.65 to 3.6
1.65
2.3
3.0
1.65 to 3.6
1.65
2. 3
3. 0
3. 6
0
3.6
3 .6
2.5
4.5
M in.
V
CC
- 0.2
1.2
1.75
2.3
V
0.2
0.4 5
0.5 5
0.7
2.5
±10
±10
40
μA
Typ.
(2)
M ax. Units
Notes:
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are measured at +25°C.
3. For I/O ports, the I
OZ
includes the input leakage current.
Timing Requirements over Operating Range
Parame te rs
De s cription
V
CC
= 1.8 V
± 0.15V
M in.
f
CLOCK
t
W
Pulse
Duration
t
SU
Setup time
Clock Frequency
LE Low
CLK High or Low
Data before CLK
↑
Data before LE
↑,
CLK High or Low
Data after CLK
↑
Data after LE
↑
, CLK High or Low
2.0
2.0
1.4
1.4
1.0
1.0
M a x.
15 0
1.2
1. 2
1. 2
1.2
0.8
0.8
V
CC
= 2.5V
± 0.2V
M in.
M ax.
150
1.0
1.0
1.0
1.0
0.6
0.6
ns
V
CC
= 3.3V
± 0.3V
M in.
M a x.
150
MHz
Units
t
H
Hold time
09-0003
5
PS8376G 10/27/09
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