AT49BV320A-80CJ datasheet, PDF

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AT49BV320A-80CJ: DescriptionFlash, 2MX16, 80ns, PBGA46, 7 X 10 MM, 1 MM HEIGHT, 0.75 MM PITCH, PLASTIC, CBGA-46; Categorystorage storage; File Size427KB，33 Pages; ManufacturerAtmel (Microchip); Environmental Compliance

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AT49BV320A-80CJ Overview

Flash, 2MX16, 80ns, PBGA46, 7 X 10 MM, 1 MM HEIGHT, 0.75 MM PITCH, PLASTIC, CBGA-46

AT49BV320A-80CJ Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Atmel (Microchip)
Parts packaging code	BGA
package instruction	7 X 10 MM, 1 MM HEIGHT, 0.75 MM PITCH, PLASTIC, CBGA-46
Contacts	46
Reach Compliance Code	compliant
ECCN code	3A991.B.1.A
Maximum access time	80 ns
Other features	TOP/BOTTOM BOOT BLOCK
Spare memory width	8
startup block	BOTTOM
JESD-30 code	R-PBGA-B46
JESD-609 code	e1
length	10 mm
memory density	33554432 bit
Memory IC Type	FLASH
memory width	16
Humidity sensitivity level	3
Number of functions	1
Number of terminals	46
word count	2097152 words
character code	2000000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	2MX16
Package body material	PLASTIC/EPOXY
encapsulated code	VFBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, VERY THIN PROFILE, FINE PITCH
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
Programming voltage	3 V
Certification status	Not Qualified
Maximum seat height	1 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	2.65 V
Nominal supply voltage (Vsup)	2.7 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	TIN SILVER COPPER
Terminal form	BALL
Terminal pitch	0.75 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	40
type	NOR TYPE
width	7 mm

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Features

•

Single Voltage Read/Write Operation: 2.65V to 3.6V

•

Access Time – 70 ns

•

Sector Erase Architecture

•

– Sixty-three 32K Word (64K Bytes) Sectors with Individual Write Lockout

– Eight 4K Word (8K Bytes) Sectors with Individual Write Lockout

Fast Word Program Time – 12 µs

Fast Sector Erase Time – 300 ms

Suspend/Resume Feature for Erase and Program

– Supports Reading and Programming from Any Sector by Suspending Erase

of a Different Sector

– Supports Reading Any Byte/Word in the Non-suspending Sectors by Suspending

Programming of Any Other Byte/Word

Low-power Operation

– 12 mA Active

– 13 µA Standby

Data Polling, Toggle Bit, Ready/Busy for End of Program Detection

VPP Pin for Write Protection

RESET Input for Device Initialization

Sector Lockdown Support

TSOP and CBGA Package Options

Top or Bottom Boot Block Configuration Available

128-bit Protection Register

Minimum 100,000 Erase Cycles

Common Flash Interface (CFI)

•

32-megabit

(2M x 16/4M x 8)

3-volt Only

Flash Memory

AT49BV320A

AT49BV320AT

AT49BV322A

AT49BV322AT

Not Recommended

for New Design

Contact

Atmel to discuss

the latest design in trends

and options

Description

The AT49BV32XA(T) is a 2.7-volt 32-megabit Flash memory organized as 2,097,152

words of 16 bits each or 4,194,304 bytes of 8 bits each. The x16 data appears on I/O0

- I/O15; the x8 data appears on I/O0 - I/O7. The memory is divided into 71 sectors for

erase operations. The device is offered in a 48-lead TSOP and a 46-ball CBGA pack-

age. The device has CE and OE control signals to avoid any bus contention. This

device can be read or reprogrammed using a single power supply, making it ideally

suited for in-system programming.

Pin Configurations

Pin Name

A0 - A20

RESET

RDY/BUSY

VPP

I/O0 - I/O14

I/O15 (A-1)

BYTE

VCCQ

Function

Addresses

Chip Enable

Output Enable

Write Enable

Reset

READY/BUSY Output

Write Protection

Data Inputs/Outputs

I/O15 (Data Input/Output, Word Mode)

A-1 (LSB Address Input, Byte Mode)

Selects Byte or Word Mode

No Connect

Output Power Supply

Rev. 3308D–FLASH–5/03

AT49BV32XA(T)

The device powers on in the read mode. Command sequences are used to place the device in

other operation modes such as program and erase. The device has the capability to protect

the data in any sector (see “Sector Lockdown” section).

To increase the flexibility of the device, it contains an Erase Suspend and Program Suspend

feature. This feature will put the erase or program on hold for any amount of time and let the

user read data from or program data to any of the remaining sectors within the memory. The

end of a program or an erase cycle is detected by the READY/BUSY pin, Data Polling or by

the toggle bit.

The VPP pin provides data protection. When the V

input is below 0.4V, the program and

erase functions are inhibited. When V

is at 0.9V or above, normal program and erase opera-

tions can be performed.

A six-byte command (Enter Single Pulse Program Mode) sequence to remove the requirement

of entering the three-byte program sequence is offered to further improve programming time.

After entering the six-byte code, only single pulses on the write control lines are required for

writing into the device. This mode (Single Pulse Byte/Word Program) is exited by powering

down the device, or by pulsing the RESET pin low for a minimum of 500 ns and then bringing

it back to V

. Erase, Erase Suspend/Resume and Program Suspend/Resume commands will

not work while in this mode; if entered they will result in data being programmed into the

device. It is not recommended that the six-byte code reside in the software of the final product

but only exist in external programming code.

When using the AT49BV320A(T) pinout configuration, the device always operates in the word

mode. In the AT49BV322A(T) configuration, the BYTE pin controls whether the device data

I/O pins operate in the byte or word configuration. If the BYTE pin is set at logic “1”, the device

is in word configuration, I/O0 - I/O15 are active and controlled by CE and OE.

If the BYTE pin is set at logic “0”, the device is in byte configuration, and only data I/O pins

I/O0 - I/O7 are active and controlled by CE and OE. The data I/O pins I/O8 - I/O14 are tri-

stated, and the I/O15 pin is used as an input for the LSB (A-1) address function.

3308D–FLASH–5/03

AT49BV32XA(T)

Device

Operation

READ:

The AT49BV32XA(T) is accessed like an EPROM. When CE and OE are low and WE

is high, the data stored at the memory location determined by the address pins are asserted

on the outputs. The outputs are put in the high impedance state whenever CE or OE is high.

This dual-line control gives designers flexibility in preventing bus contention.

COMMAND SEQUENCES:

When the device is first powered on, it will be reset to the read or

standby mode, depending upon the state of the control line inputs. In order to perform other

device functions, a series of command sequences are entered into the device. The command

sequences are shown in the “Command Definition in Hex” table on page 13 (I/O8 - I/O15 are

don’t care inputs for the command codes). The command sequences are written by applying a

low pulse on the WE or CE input with CE or WE low (respectively) and OE high. The address

is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the

first rising edge of CE or WE. Standard microprocessor write timings are used. The address

locations used in the command sequences are not affected by entering the command

sequences.

RESET:

A RESET input pin is provided to ease some system applications. When RESET is at

a logic high level, the device is in its standard operating mode. A low level on the RESET input

halts the present device operation and puts the outputs of the device in a high impedance

state. When a high level is reasserted on the RESET pin, the device returns to the read or

standby mode, depending upon the state of the control inputs.

ERASURE:

Before a byte/word can be reprogrammed, it must be erased. The erased state of

memory bits is a logical “1”. The entire device can be erased by using the Chip Erase com-

mand or individual sectors can be erased by using the Sector Erase command.

CHIP ERASE:

The entire device can be erased at one time by using the six-byte chip erase

software code. After the chip erase has been initiated, the device will internally time the erase

operation so that no external clocks are required. The maximum time to erase the chip is t

If the sector lockdown has been enabled, the chip erase will not erase the data in the sector

that has been locked out; it will erase only the unprotected sectors. After the chip erase, the

device will return to the read or standby mode.

SECTOR ERASE:

As an alternative to a full chip erase, the device is organized into 71 sec-

tors (SA0 - SA70) that can be individually erased. The Sector Erase command is a six-bus

cycle operation. The sector address is latched on the falling WE edge of the sixth cycle while

the 30H data input command is latched on the rising edge of WE. The sector erase starts after

the rising edge of WE of the sixth cycle. The erase operation is internally controlled; it will

automatically time to completion. The maximum time to erase a sector is t

SEC

. When the sec-

tor programming lockdown feature is not enabled, the sector will erase (from the same Sector

Erase command). An attempt to erase a sector that has been protected will result in the oper-

ation terminating immediately.

BYTE/WORD PROGRAMMING:

Once a memory block is erased, it is programmed (to a logi-

cal “0”) on a byte-by-byte or on a word-by-word basis. Programming is accomplished via the

internal device command register and is a four-bus cycle operation. The device will automati-

cally generate the required internal program pulses.

3308D–FLASH–5/03

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