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Datasheet> All Categories > logic> logic> IDT74LVC16952APAG8
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IDT74LVC16952APAG8

Description
Registered Bus Transceiver, LVC/LCX/Z Series, 2-Func, 8-Bit, True Output, CMOS, PDSO56, 0.50 MM PITCH, TSSOP-56
Categorylogic    logic   
File Size75KB，6 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance  
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IDT74LVC16952APAG8 Overview

Registered Bus Transceiver, LVC/LCX/Z Series, 2-Func, 8-Bit, True Output, CMOS, PDSO56, 0.50 MM PITCH, TSSOP-56

IDT74LVC16952APAG8 Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
Parts packaging codeTSSOP
package instructionTSSOP,
Contacts56
Reach Compliance Codecompliant
Other featuresWITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION
seriesLVC/LCX/Z
JESD-30 codeR-PDSO-G56
JESD-609 codee3
length14 mm
Logic integrated circuit typeREGISTERED BUS TRANSCEIVER
Humidity sensitivity level1
Number of digits8
Number of functions2
Number of ports2
Number of terminals56
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Output characteristics3-STATE
Output polarityTRUE
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)260
propagation delay (tpd)7.6 ns
Certification statusNot Qualified
Maximum seat height1.2 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)2.7 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceMatte Tin (Sn) - annealed
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
width6.1 mm

IDT74LVC16952APAG8 Preview

IDT74LVC16952A
3.3V CMOS 16-BIT REGISTERED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS 16-BIT
REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS,
5 VOLT TOLERANT I/O
• Typical t
SK(o)
(Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• V
CC
= 3.3V ± 0.3V, Normal Range
• V
CC
= 2.7V to 3.6V, Extended Range
• CMOS power levels (0.4µ W typ. static)
µ
• All inputs, outputs, and I/O are 5V tolerant
• Supports hot insertion
• Available in SSOP, TSSOP, and TVSOP packages
IDT74LVC16952A
FEATURES:
DESCRIPTION:
DRIVE FEATURES:
APPLICATIONS:
• High Output Drivers: ±24mA
• Reduced system switching noise
This 16-bit registered transceiver is built using advanced dual metal
CMOS technology. This high-speed, low power device is organized as two
independent 8-bit D-type registered transceivers with separate input and
output control for independent control of data flow in either direction. For
example, the A-to-B Enable (CEAB) must be LOW to enter data from the A
port. CLKAB controls the clocking function. When CLKAB toggles from LOW-
to-HIGH, the data present on the A port will be clocked into the register.
OEAB
performs the output enable function on the B port. Data flow from the
B port to A port is similar but requires using
CEBA,
CLKBA, and
OEBA
inputs.
Full 16-bit operation is achieved by tying the control pins of the independent
transceivers together.
All pins can be driven from either 3.3V or 5V devices. This feature allows
the use of this device as a translator in a mixed 3.3V/5V supply system.
The LVC16952A has been designed with a
±
24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
FUNCTIONAL BLOCK DIAGRAM
54
1
CEBA
1
CLKBA
1
OEAB
1
CEAB
1
CLKAB
1
OEBA
3
55
1
2
OEAB
2
CEAB
2
CLKAB
2
OEBA
2
CEBA
2
CLKBA
31
30
28
26
27
2
56
29
1
A
1
5
C
CE
D
C
CE
D
52
1
B
1
2
A
1
15
C
CE
D
C
CE
D
42
2
B
1
TO SEVEN OTHER CHANNELS
TO SEVEN OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
© 1999 Integrated Device Technology, Inc.
MARCH 1999
DSC-4492/2
IDT74LVC16952A
3.3V CMOS 16-BIT REGISTERED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
1
OEAB
1
CLKAB
1
CEAB
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Description
Max
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
Unit
V
°C
mA
mA
mA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
V
TERM
1
OEBA
1
CLKBA
1
CEBA
Terminal Voltage with Respect to GND
Storage Temperature
DC Output Current
Continuous Clamp Current,
V
I
< 0 or V
O
< 0
Continuous Current through each
V
CC
or GND
–0.5 to +6.5
–65 to +150
–50 to +50
–50
±100
T
STG
I
OUT
I
IK
I
OK
I
CC
I
SS
GND
1
A
1
1
A
2
GND
1
B
1
1
B
2
V
CC
1
A
3
1
A
4
1
A
5
V
CC
1
B
3
1
B
4
1
B
5
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
GND
1
A
6
1
A
7
1
A
8
2
A
1
2
A
2
2
A
3
GND
1
B
6
1
B
7
1
B
8
2
B
1
2
B
2
2
B
3
PIN DESCRIPTION
Pin Names
xOEAB
xOEBA
xCEAB
xCEBA
xCLKAB
xCLKBA
xAx
xBx
Description
A-to-B Output Enable Inputs (Active LOW)
B-to-A Output Enable Inputs (Active LOW)
A-to-B Clock Enable Inputs (Active LOW)
B-to-A Clock Enable Inputs (Active LOW)
A-to-B Clock Inputs
B-to-A Clock Inputs
A-to-B Data Inputs or B-to-A 3-State Outputs
B-to-A Data Inputs or A-to-B 3-State Outputs
GND
2
A
4
2
A
5
2
A
6
GND
2
B
4
2
B
5
2
B
6
V
CC
2
A
7
2
A
8
V
CC
2
B
7
2
B
8
GND
2
CEAB
2
CLKAB
2
OEAB
GND
2
CEBA
2
CLKBA
2
OEBA
FUNCTION TABLE
(1,2)
Inputs
xCEAB
xCLKAB
X
L
↑
↑
X
xOEAB
L
L
L
L
H
xAx
X
X
L
H
X
H
X
L
L
Outputs
xBx
B
(3)
B
(3)
L
H
Z
SSOP/ TSSOP/ TVSOP
TOP VIEW
CAPACITANCE
(T
A
= +25°C, F = 1.0MHz)
Symbol
C
IN
C
OUT
C
I/O
Parameter
(1)
Input Capacitance
Output Capacitance
I/O Port Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
V
IN
= 0V
Typ.
4.5
6.5
6.5
Max.
6
8
8
Unit
pF
pF
pF
X
NOTE:
1. As applicable to the device type.
NOTES:
1. A-to-B data flow is shown: B-to-A data flow is similar but uses xCEBA, xCLKBA,
and xOEBA.
2. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High Impedance
↑
= LOW-to-HIGH Transition
3. Output level of B before the indicated steady-state input conditions were established.
2
IDT74LVC16952A
3.3V CMOS 16-BIT REGISTERED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: T
A
= –40°C to +85°C
Symbol
V
IH
V
IL
I
IH
I
IL
I
OZH
I
OZL
I
OFF
V
IK
V
H
I
CCL
I
CCH
I
CCZ
∆I
CC
High Impedance Output Current
(3-State Output pins)
Input/Output Power Off Leakage
Clamp Diode Voltage
Input Hysteresis
Quiescent Power Supply Current
V
CC
= 0V, V
IN
or V
O
≤
5.5V
V
CC
= 2.3V, I
IN
= –18mA
V
CC
= 3.3V
V
CC
= 3.6V
V
IN
= GND or V
CC
—
—
—
—
—
—
—
–0.7
100
—
—
—
±50
–1.2
—
10
10
500
µA
V
mV
µA
V
CC
= 3.6V
V
O
= 0 to 5.5V
—
—
±10
µA
Parameter
Input HIGH Voltage Level
Input LOW Voltage Level
Input Leakage Current
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 3.6V
V
I
= 0 to 5.5V
Test Conditions
Min.
1.7
2
—
—
—
Typ.
(1)
—
—
—
—
—
Max.
—
—
0.7
0.8
±5
µA
V
Unit
V
Quiescent Power Supply Current
Variation
3.6
≤
V
IN
≤
5.5V
(2)
One input at V
CC
- 0.6V, other inputs at V
CC
or GND
µA
NOTES:
1. Typical values are at V
CC
= 3.3V, +25°C ambient.
2. This applies in the disabled state only.
OUTPUT DRIVE CHARACTERISTICS
Symbol
V
OH
Parameter
Output HIGH Voltage
V
CC
= 2.3V
V
CC
= 2.3V
V
CC
= 2.7V
V
CC
= 3V
V
CC
= 3V
V
OL
Output LOW Voltage
V
CC
= 2.3V to 3.6V
V
CC
= 2.3V
V
CC
= 2.7V
V
CC
= 3V
I
OH
= – 24mA
I
OL
= 0.1mA
I
OL
= 6mA
I
OL
= 12mA
I
OL
= 12mA
I
OL
= 24mA
Test Conditions
(1)
V
CC
= 2.3V to 3.6V
I
OH
= – 0.1mA
I
OH
= – 6mA
I
OH
= – 12mA
Min.
V
CC
– 0.2
2
1.7
2.2
2.4
2.2
—
—
—
—
—
Max.
—
—
—
—
—
—
0.2
0.4
0.7
0.4
0.55
V
Unit
V
NOTE:
1. V
IH
and V
IL
must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate V
CC
range.
T
A
= – 40°C to + 85°C.
3
IDT74LVC16952A
3.3V CMOS 16-BIT REGISTERED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
OPERATING CHARACTERISTICS, V
CC
= 3.3V ± 0.3V, T
A
= 25°C
Symbol
C
PD
C
PD
Parameter
Power Dissipation Capacitance per Latch Outputs enabled
Power Dissipation Capacitance per Latch Outputs disabled
Test Conditions
C
L
= 0pF, f = 10Mhz
Typical
87
43
Unit
pF
SWITCHING CHARACTERISTICS
(1)
V
CC
= 2.7V
Symbol
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
SU
t
H
t
SU
t
H
t
W
t
SK
(o)
Parameter
Propagation Delay
xCLKAB, xCLKBA to xBx, xAx
Output Enable Time
xOEBA, xOEAB to xAx, xBx
Output Disable Time
xOEBA, xOEAB to xAx, xBx
Set-up Time, HIGH or LOW
xAx, xBx before xCLKAB↑, xCLKBA↑
Hold Time, HIGH or LOW
xAx, xBx after xCLKAB↑, xCLKBA↑
Set-up Time, HIGH or LOW
xCEAB, xCEBA before xCLKAB↑, xCLKBA↑
Hold Time, HIGH or LOW
xCEAB, xCEBA after xCLKAB↑, xCLKBA↑
xLE Pulse Width HIGH or LOW, xCLKAB or xCLKBA
Output Skew
(2)
3.3
—
—
—
3.3
—
—
500
ns
ps
1.1
—
1.9
—
ns
1.8
—
1.4
—
ns
0.5
—
0.5
—
ns
3.4
—
2.8
—
ns
—
7.1
1.9
6.7
ns
—
8
1.1
6.6
ns
Min.
—
Max.
7.6
V
CC
= 3.3V ± 0.3V
Min.
1.6
Max.
6.6
Unit
ns
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. T
A
= – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
4
IDT74LVC16952A
3.3V CMOS 16-BIT REGISTERED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
TEST CONDITIONS
Symbol
V
LOAD
V
IH
V
T
V
LZ
V
HZ
C
L
V
CC(1)
= 3.3V±0.3V
6
2.7
1.5
300
300
50
V
CC
500Ω
Pulse
(1, 2)
Generator
V
IN
D.U.T.
R
T
500Ω
C
L
LVC Link
V
CC(1)
= 2.7V
6
2.7
1.5
300
300
50
V
CC(2)
= 2.5V±0.2V
2 x Vcc
Vcc
Vcc / 2
150
150
30
Unit
V
V
V
mV
mV
pF
V
LOAD
Open
GND
SAME PHASE
INPUT TRANSITION
t
PLH
OUTPUT
t
PLH
OPPOSITE PHASE
INPUT TRANSITION
t
PHL
t
PHL
V
IH
V
T
0V
V
OH
V
T
V
OL
V
IH
V
T
0V
LVC Link
Propagation Delay
ENABLE
CONTROL
INPUT
t
PZL
OUTPUT
SWITCH
NORMALLY
CLOSED
LOW
t
PZH
OUTPUT
SWITCH
NORMALLY
OPEN
HIGH
V
LOAD/2
V
T
t
PHZ
V
T
0V
t
PLZ
DISABLE
V
IH
V
T
0V
V
LOAD/2
V
OL+
V
LZ
V
OL
V
OH
V
OH-
V
HZ
0V
LVC Link
V
OUT
Test Circuit for All Outputs
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
= Termination resistance: should be equal to Z
OUT
of the Pulse Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate
≤
10MHz; t
F
≤
2.5ns; t
R
≤
2.5ns.
2. Pulse Generator for All Pulses: Rate
≤
10MHz; t
F
≤
2ns; t
R
≤
2ns.
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
Enable and Disable Times
SWITCH POSITION
Test
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other Tests
Switch
V
LOAD
GND
Open
V
IH
V
T
0V
V
OH
V
T
V
OL
V
OH
V
T
V
OL
t
PLH2
t
PHL2
LVC Link
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS
CONTROL
SYNCHRONOUS
CONTROL
t
SU
t
H
t
REM
t
SU
t
H
V
IH
V
T
0V
V
IH
V
T
0V
V
IH
V
T
0V
V
IH
V
T
0V
LVC Link
INPUT
Set-up, Hold, and Release Times
LOW-HIGH-LOW
PULSE
t
W
HIGH-LOW-HIGH
PULSE
V
T
LVC Link
t
PLH1
t
PHL1
OUTPUT 1
V
T
t
SK
(x)
t
SK
(x)
OUTPUT 2
t
SK
(x)
= t
PLH2
-
t
PLH1
or
t
PHL2
-
t
PHL1
Pulse Width
Output Skew - t
SK
(
X
)
NOTES:
1. For t
SK
(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For t
SK
(b) OUTPUT1 and OUTPUT2 are in the same bank.
5
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IDT74LVC16952APAG8 Related Products

IDT74LVC16952APAG8 IDT74LVC16952APFG8 IDT74LVC16952APVG8
Description Registered Bus Transceiver, LVC/LCX/Z Series, 2-Func, 8-Bit, True Output, CMOS, PDSO56, 0.50 MM PITCH, TSSOP-56 Registered Bus Transceiver, LVC/LCX/Z Series, 2-Func, 8-Bit, True Output, CMOS, PDSO56, 0.40 MM PITCH, TVSOP-56 Registered Bus Transceiver, LVC/LCX/Z Series, 2-Func, 8-Bit, True Output, CMOS, PDSO56, 0.635 MM PITCH, SSOP-56
Is it lead-free? Lead free Lead free Lead free
Is it Rohs certified? conform to conform to conform to
Maker IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology)
Parts packaging code TSSOP SSOP SSOP
package instruction TSSOP, TSSOP, SSOP,
Contacts 56 56 56
Reach Compliance Code compliant compliant compliant
Other features WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION
series LVC/LCX/Z LVC/LCX/Z LVC/LCX/Z
JESD-30 code R-PDSO-G56 R-PDSO-G56 R-PDSO-G56
JESD-609 code e3 e3 e3
length 14 mm 11.3 mm 18.415 mm
Logic integrated circuit type REGISTERED BUS TRANSCEIVER REGISTERED BUS TRANSCEIVER REGISTERED BUS TRANSCEIVER
Humidity sensitivity level 1 1 1
Number of digits 8 8 8
Number of functions 2 2 2
Number of ports 2 2 2
Number of terminals 56 56 56
Maximum operating temperature 85 °C 85 °C 85 °C
Minimum operating temperature -40 °C -40 °C -40 °C
Output characteristics 3-STATE 3-STATE 3-STATE
Output polarity TRUE TRUE TRUE
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code TSSOP TSSOP SSOP
Package shape RECTANGULAR RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, SHRINK PITCH
Peak Reflow Temperature (Celsius) 260 260 260
propagation delay (tpd) 7.6 ns 7.6 ns 7.6 ns
Certification status Not Qualified Not Qualified Not Qualified
Maximum seat height 1.2 mm 1.2 mm 2.794 mm
Maximum supply voltage (Vsup) 3.6 V 3.6 V 3.6 V
Minimum supply voltage (Vsup) 2.7 V 2.7 V 2.7 V
Nominal supply voltage (Vsup) 3.3 V 3.3 V 3.3 V
surface mount YES YES YES
technology CMOS CMOS CMOS
Temperature level INDUSTRIAL INDUSTRIAL INDUSTRIAL
Terminal surface Matte Tin (Sn) - annealed Matte Tin (Sn) - annealed MATTE TIN
Terminal form GULL WING GULL WING GULL WING
Terminal pitch 0.5 mm 0.4 mm 0.635 mm
Terminal location DUAL DUAL DUAL
Maximum time at peak reflow temperature 30 30 30
width 6.1 mm 4.4 mm 7.5 mm

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