21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C2520
Low-Noise Phase-Locked Loop
Clock Driver with 20 Clock Outputs
Product Features
Low-Noise Phase-Locked Loop Clock Distribution.
Allows Clock Input to have Spread Spectrum modulation
for EMI reduction. The clock outputs track the Clock Input
modulation.
Maximum clock frequency of 125 MHz.
Zero Input-to-Output delay.
Low jitter: Cycle-to-Cycle jitter ±100ps max.
On-chip series damping resistor at clock output drivers for
low noise and EMI reduction.
Operates at 3.3V V
CC
.
Output-to-Output skew less than 200ps.
Package: Plastic 56-pin TSSOP (A).
Product Description
The PI6C2520 is a low-skew, low-jitter, phase-locked loop (PLL)
clock driver, distributing low-noise clock signals for Networking
Applications. By connecting the feedback FB_OUT output to the
feedback FB_IN input, the propagation delay from the CLK_IN
input to any clock output will be nearly zero. This zero-delay
feature allows the CLK_IN input clock to be distributed, providing
5 banks of 4 clocks and an extra clock for feedback.
For test purposes, the PLL can be bypassed by strapping AV
CC
to
ground. The PI6C2520, which allows a Spread Spectrum clock in-
put, operates at 3.3V V
CC
and provides integrated series-damping
resistors that make it ideal for driving point-to-point loads. Output
signal duty cycles are adjusted to 50 percent, independent of the
duty cycle at the input clock.
Each bank of outputs can be enabled or disabled via the 1G, 2G,
3G, 4G, and 5G control inputs. When the G inputs are high, the
outputs switch in phase and frequency with CLK_IN. When the G
inputs are low, the outputs are disabled to the logic low state.
Product Pin Configuration
VCC
1Y0
1Y1
GND
GND
1Y2
1Y3
VCC
1G
GND
AVCC
CLK_IN
AGND
5G
GND
2G
VCC
2Y0
2Y1
GND
GND
2Y2
2Y3
VCC
VCC
5Y0
5Y1
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VCC
4Y0
4Y1
GND
GND
4Y2
4Y3
VCC
4G
GND
AVCC
FB_IN
AGND
FB_OUT
GND
3G
VCC
3Y0
3Y1
GND
GND
3Y2
3Y3
VCC
VCC
5Y3
5Y2
GND
Block Diagram
1G
2G
3G
4G
5G
4
4
4
4
1Y [0:3]
2Y [0:3]
3Y [0:3]
4Y [0:3]
56-Pin
A
CLK_IN
PLL
FB_IN
AVCC
4
5Y [0:3]
FB_OUT
1
PS8435B
07/25/00
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C2520
Low-Noise, Phase-Locked Loop
Clock Driver with 20 Clock Outputs
Pin Functions
Pin Name
CLK _IN
FB_IN
1G
2G
3G
4G
5G
FB_O UT
1Y[0:3]
2Y[0:3]
3Y[0:3]
4Y[0:3]
5Y[0:3]
AV
CC
AGND
V
CC
GND
Pin Numbe r
12
45
9
16
41
48
14
43
2,3,6,7
18,19,22,23
39,38,35,34
55,54.51,50
26,27,30,31
11,46
13,44
1,8,17,24,25,32,33,40,
49,56
4,5,10,15,20,21,28,29,
36,37,42,47,52,53
Type
I
I
I
I
I
I
I
O
O
O
O
O
O
Power
D e s cription
Clock input. CLK allows spread spectrum.
Feedback input. FB_IN provides the feedback signal to the internal PLL.
O utput bank enable. When 1G is LO W, outputs 1Y[0:3] are disabled to
a logic low state. When 1G is HIGH, all outputs 1Y[0:3] are enabled.
O utput bank enable. When 2G is LO W, outputs 2Y[0:3] are disabled to
a logic low state. When 2G is HIGH, all outputs 2Y[0:3] are enabled.
O utput bank enable. When 3G is LO W, outputs 3Y[0:3] are disabled to
a logic low state. When 3G is HIGH, all outputs 3Y[0:3] are enabled.
O utput bank enable. When 4G is LO W, outputs 4Y[0:3] are disabled to
a logic low state. When 4G is HIGH, all outputs 4Y[0:3] are enabled.
O utput bank enable. When 5G is LO W, outputs 5Y[0:3] are disabled to
a logic low state. When 5G is HIGH, all outputs 5Y[0:3] are enabled.
Feedback output. FB_O UT is dedicated for external feedback. FB_O UT
has an embedded series- damping resistor of the same value as the clock outputs
1Yx, 2Yx, 3Yx, 4Yx, and 5Yx.
Clock outputs. These outputs provide low- skew copies of CLK .
Each output has an embedded series- damping resistor.
Clock outputs. These outputs provide low- skew copies of CLK .
Each output has an embedded series- damping resistor.
Clock outputs. These outputs provide low- skew copies of CLK .
Each output has an embedded series- damping resistor.
Clock outputs. These outputs provide low- skew copies of CLK .
Each output has an embedded series- damping resistor.
Clock outputs. These outputs provide low- skew copies of CLK .
Each output has an embedded series- damping resistor.
Analog power supply. AV
CC
can be also used to bypass the PLL for
test purposes. When AV
CC
is strapped to ground, PLL is bypassed and
CLK is buffered directly to the device outputs.
Ground Analog ground. AGND provides the ground reference for the analog circuitry
Power
Power supply
Ground Ground
2
PS8435B
07/25/00
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C2520
Low-Noise, Phase-Locked Loop
Clock Driver with 20 Clock Outputs
Absolute Maximum Ratings
(Over Operating Free-Air Temperature, unless otherwise noted)
Supply voltage range, V
CC ...................................................................................................................................................
0.5V to 4.6V
Input voltage range, V
I (1) ....................................................................................................................................................
0.5V to 6.5V
Voltage range applied to any output in the high or low state, V
O(1,2) ...................................................
0.5V to V
CC
+0.5V
Input clamp current, I
IK
(V
I
<0) ......................................................................................................................... 50mA
Output clamp current, I
OK
(V
O
<0 or V
O
> V
CC
) ............................................................................................... ±50mA
Continuous output current, I
O
(V
O
- 0 to V
CC
) ................................................................................................. ±50mA
Continuous current through each V
CC
or GND .............................................................................................. ±100mA
Maximum power dissipation at T
A
= 55°C (in still air)
(3) ........................................................................................................
0.85W
Storage Temperature Range, T
stg ...................................................................................................................................
65°C to 150°C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated under "Recommended Operating Conditions" is not implied. Exposure
to Absolute-Maximum-Rated conditions for extended periods may affect device reliability.
Notes:
1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This value is limited to 4.6V maximum.
3. Maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
Recommended Operating Conditions
(4)
Symbol
V
CC
V
IH
V
IL
V
I
I
OH
I
OL
T
A
Supply voltage
High- level input voltage
Low- level input voltage
Input Voltage
High- level output current
Low- level output current
Operating free- air temperature
0
0
Parame te r
M in.
3
2
0.8
V
CC
12
12
70
mA
°C
M ax.
3.6
V
Units
Notes:
4. Unused inputs must be held high or low to prevent them from floating.
Function Table
xG
L
L
H
H
Note:
x is from 1 to 5
CLK_IN
L
H
L
H
xY [0:3]
L
L
L
H
FB_OUT
L
H
L
H
3
PS8435B
07/25/00
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C2520
Low-Noise, Phase-Locked Loop
Clock Driver with 20 Clock Outputs
Electrical Characteristics
(Over Recommended Operating Free-air Temperature Range, unless otherwise noted)
Symbol
V
IK,
Input clamp voltage
V
OH
Te s t Condition
Input current at 18mA
I
OH
= 100µA
I
OH
= 12mA
I
OH
= 6mA
I
OL
= 100µA
V
OL
I
I,
Input current
I
CC,
Analog supply current
C
i
C
O
∆I
CC
I
OL
= 12mA
I
OL
= 6mA
Clock input voltage = V
CC
or GND
Clock input voltage = V
CC
or GND
Input voltage = V
CC
or GND
O utput voltage = V
CC
or GND
O ne input @ V
CC
0.6V,
other inputs @ V
CC
or GND
V
CC
3V
Min. to Max.
3V
Min. to Max.
3V
3.6V
3.3V
3.3V to 3.6V
4
6
4.0
500
µA
V
CC
0.2
2.1
2.4
M in.
Typ.
(1)
0.79
2.99
2.66
2.83
0.01
0.3
0.15
0.2
0.8
0.55
±5
20
3.5
µA
pF
V
M ax.
1.2
Units
Notes:
1. For Min. or Max. conditions, use the appropriate value specified under recommended operating conditions.
Timing Requirements
(Over Recommended Ranges of Supply Voltage and Operating Free-Air Temperature).
Symbol
F
CLK
D
CYI
t
Stabilization
Clock Frequency
Input clock duty cycle
Stabilization Time after power up
Parame te r
M in.
25
40
M ax.
125
60
1
Units
MHz
%
ms
Note
1
Switching Characteristics
(Over
Recommended Ranges of Supply Voltage & Operating Free-Air Temperature, C
L
= 22pF)
(1,3)
V
CC
= 3.3V ± 0.3V
Parame te r
t
phase
error
t
sk(O)(2)
Jitter
(pk- pk)
Duty cycle
t
r
t
f
From (Input)
CLK_IN
↑
= 100MHz
Any Y or FBOUT
F(CLK_IN> 66MHz)
F(CLK_IN
≤
66MHz)
F(CLK_IN > 66MHz)
Measured from 20% to 80%
Any Y or FB_OUT
100
45
45
0.7
1.2
To (Output)
FB_IN
↑
M in.
Typ.
170
200
100
55
55
2.8
2.8
%
ns
ps
M ax.
Units
Notes:
1. These parameters are not production tested.
2. The t
sk(o)
specification is only valid for equal loading of all outputs.
3. The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed.
4
PS8435B
07/25/00
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C2520
Low-Noise, Phase-Locked Loop
Clock Driver with 20 Clock Outputs
Parameter Measurement Information
3V
Input
From Output
Under Test
50% V
CC
50% V
CC
0V
t
pd
22pF
500Ω
Output
80%
20%
50% V
CC
80%
20%
V
OH
V
OL
Load Circuit
t
r
t
f
Voltage Waveforms
Propagation Delay times
Notes:
1. C
L
includes probe and jig capacitance.
2. All input pulses are supplied by generators having the following characteristics: CLK_IN
≤
100MHz, Z
O
= 50 ohms, t
r
≤
1.2ns, t
f
≤
1.2ns.
3. The outputs are measured one at a time with one transition per measurement.
CLK_IN
FB_IN
t
phase
error
FB_OUT
Any Y
t
sk(O)
Any Y
Any Y
t
sk(O)
Phase Error and Skew Calculations
5
PS8435B
07/25/00
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