19-2236; Rev 0; 10/01
Single-Ended-to-Differential
LVECL/LVPECL 2:1 Multiplexer
General Description
The MAX9380 is a high-speed, low-jitter 2:1 multiplexer
for clock and data distribution applications. The device
selects one of the two single-ended inputs and con-
verts it to a differential output.
The MAX9380 features low part-to-part skew of 33ps
and propagation delay of 263ps.
The MAX9380 operates from a +3.0V to +3.8V supply for
LVPECL applications or from a -3.0V to -3.8V supply for
LVECL applications. The input is selected by a single select
input. The select and data inputs feature internal pulldown
resistors that ensure a low default state if left open.
These devices are specified for operation from -40°C to
+85°C, and are available in space-saving 8-pin µMAX
and SO packages.
o
Low 20mA Supply Current
o
33ps (typ) Part-to-Part Skew
o
263ps (typ) Propagation Delay
o
<0.2ps
RMS
Added Random Jitter
o
High-Speed Select Input
o
Output Low with Open Inputs
o
Pin Compatible with MC10EP58
Features
o
>300mV Differential Output at 3.5GHz
MAX9380
Applications
Precision Clock Distribution
DSLAM
DLC
Base Station
ATE
PART
MAX9380EUA*
MAX9380ESA
Ordering Information
TEMP. RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
8 µMAX
8 SO-EP**
*Future
product—contact factory for availability.
**EP
= Exposed paddle.
Input/Output Function Table
INPUTS
Da (SEL
=
high) or
Db (SEL
=
low)
High
Low or open
Q
H
L
OUTPUTS
Pin Configuration
TOP VIEW
Q
L
H
Da
2
75kΩ
3
75kΩ
5
75kΩ
V
EE
6
Q
NC
1
8
V
CC
MAX9380
1
7
Q
Db
0
SEL
4
µMAX/SO
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Single-Ended-to-Differential
LVECL/LVPECL 2:1 Multiplexer
MAX9380
ABSOLUTE MAXIMUM RATINGS
V
CC
- V
EE
...............................................................-0.3V to +4.1V
Inputs (Da, Db, SEL).............................V
EE
- 0.3V to V
CC
+ 0.3V
Output Current (Continuous)...............................................50mA
Output Current (Surge) .....................................................100mA
Junction-to-Ambient Thermal Resistance in Still Air
8-Pin µMAX ..............................................................+221°C/W
8-Pin SO* .................................................................+170°C/W
Junction-to-Ambient Thermal Resistance with
500LFPM Airflow
8-Pin µMAX ..............................................................+155°C/W
8-Pin SO* ...................................................................+99°C/W
Junction-to-Case Thermal Resistance
8-Pin µMAX ................................................................+39°C/W
8-Pin SO.....................................................................+40°C/W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
ESD Protection
Human Body Model (Inputs and Outputs) .........................2kV
Soldering Temperature (10s) ...........................................+300°C
*
Rating is for exposed paddle not connected.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
CC
- V
EE
= +3.0V to +3.8V, outputs terminated with 50Ω to V
CC
- 2.0V, unless otherwise noted.) (Notes 1, 2, 3)
PARAMETER
SYMBOL
CONDITIONS
-40°C
MIN
V
CC
-
1.210
V
CC
-
1.935
V
IN
= V
IH(MAX)
V
IN
= V
IL(MIN)
0.5
TYP
MAX
MIN
+25°C
TYP
MAX
MIN
+85°C
TYP
MAX
V
CC
-
0.760
V
CC
-
1.485
150
0.5
UNITS
INPUTS (Da, Db, SEL)
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
OUTPUTS (Q,
Q)
Single-Ended
Output High
Voltage
Single-Ended
Output Low
Voltage
Differential Output
Voltage
POWER SUPPLY
Supply Current
I
EE
(Note 4)
18
26
20
26
22
30
mA
V
OH
Figure 1
V
CC
- V
CC
- V
CC
- V
CC
- V
CC
- V
CC
- V
CC
- V
CC
- V
CC
-
1.135 0.979 0.885 1.07 0.959 0.82 1.01 0.947 0.76
V
V
IH
V
IL
I
IH
I
IL
V
CC
- V
CC
-
0.885 1.145
V
CC
- V
CC
-
1.610 1.870
150
0.5
V
CC
- V
CC
-
0.820 1.085
V
CC
- V
CC
-
1.545 1.81
150
V
V
µA
µA
V
OL
V
OH
-
V
OL
Figure 1
V
CC
- V
CC
- V
CC
-
1.935 1.721 1.685
550
748
V
CC
- V
CC
- V
CC
- V
CC
- V
CC
- V
CC
-
1.87 1.698 1.62 1.81 1.681 1.56
550
741
550
734
V
Figure 1
mV
2
_______________________________________________________________________________________
Single-Ended-to-Differential
LVECL/LVPECL 2:1 Multiplexer
AC ELECTRICAL CHARACTERISTICS
(V
CC
- V
EE
= +3.0V to +3.8V, outputs loaded with 50Ω to V
CC
- 2V, V
IH
= V
CC
- 1.11V, V
IL
= V
CC
- 1.53V, input frequency = 2.0GHz,
input transition time = 125ps (20% to 80%). Typical values are at V
CC
- V
EE
= +3.3V, unless otherwise noted.) (Notes 1, 5)
PARAMETER
Data Input-to-Output
Delay
Select Input-to-
Output Delay
Part-to-Part Skew
Added Random
Jitter (Note 7)
SYMBOL
t
PLH1
,
t
PHL1
t
PLH2
,
t
PHL2
,
t
SKPP
t
RJ
CONDITIONS
Figure 1
Figure 2
Data input to
output (Note 6)
f
IN
= 3.2GHz,
clock pattern
2.0Gbps, 2
23
- 1
PRBS
t
DJ
3.2Gbps, 2 - 1
PRBS
V
OH
- V
OL
≥
Figure 300mV
1
V
OH
- V
OL
≥
550mV
Output Rise/Fall
Time (20% to 80%)
t
R
, t
F
Figure 1
3.0
2.0
50
96
3.5
23
MAX9380
-40°C
MIN
176
210
TYP
258
304
27
MAX
298
329
122
1.2
51
77
3.0
2.0
50
MIN
192
219
+25°C
TYP
263
308
33
0.2
36
48
3.5
MAX
316
360
124
1.2
51
77
3.0
2.0
96
50
MIN
222
247
+85°C
TYP
277
318
14
MAX
385
392
163
1.2
51
UNITS
ps
ps
ps
ps
(RMS)
Added Deterministic
Jitter (Note 7)
ps
(p-p)
77
3.5
GHz
Switching Frequency
f
MAX
98
ps
Note 1:
Measurements are made with the device in thermal equilibrium.
Note 2:
Current into a pin is defined as positive. Current out of a pin is defined as negative.
Note 3:
DC parameters are production tested at +25°C. DC limits are guaranteed by design and characterization over the full oper-
ating temperature range.
Note 4:
All pins are open except V
CC
and V
EE
.
Note 5:
Guaranteed by design and characterization. Limits are set to ±6 sigma.
Note 6:
Measured between outputs of different parts at the signal crossing points under identical conditions for a same-edge transition.
Note 7:
Device jitter added to the input signal.
_______________________________________________________________________________________
3
Single-Ended-to-Differential
LVECL/LVPECL 2:1 Multiplexer
MAX9380
Typical Operating Characteristics
(V
CC
- V
EE
= +3.3V, V
IH
= V
CC
- 1.165V, V
IL
= V
CC
- 1.475V, outputs loaded with 50Ω to V
CC
- 2.0V, input frequency = 1GHz, input
transition time = 125ps (20% to 80%), unless otherwise noted.)
SUPPLY CURRENT (I
EE
)
vs. TEMPERATURE
MAX9380 toc01
OUTPUT AMPLITUDE (V
OH
- V
OL
)
vs. FREQUENCY
MAX9380 toc02
30
1.00
SUPPLY CURRENT (mA)
25
OUTPUT AMPLITUDE (V)
0.80
20
0.60
15
0.40
10
-40
-15
10
35
60
85
TEMPERATURE (°C)
0.20
0
500
1000 1500 2000 2500 3000 3500
FREQUENCY (MHz)
OUTPUT RISE/FALL TIME
vs. TEMPERATURE
MAX9380 toc03
PROPAGATION DELAY
vs. TEMPERATURE
MAX9380 toc04
100
95
90
85
80
75
70
-40
-15
10
35
60
t
R
t
F
320
300
PROPAGATION DELAY (ps)
280
260
240
220
200
180
t
PHL1
OUTPUT RISE/FALL TIME (ps)
t
PLH1
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
4
_______________________________________________________________________________________
Single-Ended-to-Differential
LVECL/LVPECL 2:1 Multiplexer
Pin Description
PIN
1
2
3
4
5
6
7
8
Exposed
Paddle
NAME
NC
Da
Db
SEL
V
EE
Q
Q
V
CC
EP
No Connection. Not internally connected.
Single-Ended LVECL/LVPECL Data Input. Da is low default through internal 75kΩ pulldown resistor.
Single-Ended LVECL/LVPECL Data Input. Db is low default through internal 75kΩ pulldown resistor.
Single-Ended Control Input. SEL is low default through an internal 75kΩ pulldown resistor selecting Db.
Setting SEL to high selects Da.
Negative Supply Voltage
Differential LVECL/LVPECL Output. Open Emitter.
Q
is default high when inputs are open.
Differential LVECL/LVPECL Output. Open Emitter. Q is default low when inputs are open.
Positive Supply Voltage. Bypass V
CC
to V
EE
with 0.1µF and 0.01µF capacitors as close to the device as
possible, with the smaller capacitor closest to the IC.
Exposed paddle (MAX9380ESA-EP only). Connect to V
EE
internally. See package dimension.
FUNCTION
MAX9380
V
IH
50%
Da WHEN SEL = HIGH
OR
Db WHEN SEL = LOW
t
PLH1
Q
SINGLE-ENDED WAVEFORMS
Q
V
OH
- V
OL
50%
V
IL
t
PHL1
V
OH
V
OL
80%
V
OH
- V
OL
80%
0 (DIFFERENTIAL)
DIFFERENTIAL WAVEFORM
Q-Q
20%
V
OH
- V
OL
20%
t
R
t
F
Figure 1. Data Input-to-Output Propagation Delay and Transition Timing Diagram
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5
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