L5380/53C80
DEVICES INCORPORATED
SCSI Bus Controller
L5380/53C80
DEVICES INCORPORATED
SCSI Bus Controller
DESCRIPTION
The
L5380/53C80
are high perform-
ance SCSI bus controllers which
support the physical layer of the SCSI
(Small Computer System Interface)
bus as defined by the ANSI X3T9.2
committee. It is pin and functionally
compatible with the NMOS NCR5380,
while offering up to a 2.5x perform-
ance improvement, 10x power reduc-
tion, and lower cost. Replacement of
the NMOS 5380 by the LOGIC Devices
L5380/53C80 will result in an imme-
diate transfer rate improvement due
to REQ/ACK and DRQ/DACK
handshake response times up to 5
times faster than previous devices.
While remaining firmware compatible
with the NCR5380, the L5380/53C80
provides bug fixes and state machine
enhancements allowing even larger
throughput gains for new designs.
The L5380/53C80 supports asynchro-
nous data transfer between initiator
and target at up to 4 Mbytes/sec. It
operates in either initiator or target
roles and offers a choice of program-
med I/O (direct microprocessor
manipulation of handshake) or any of
several DMA modes (autonomous
handshake and data transfer opera-
tions). The L5380/53C80 has internal
hardware to support arbitration and
can monitor and generate interrupts
for a variety of error conditions. It
provides extensive bus status monitor-
ing features and includes buffers
capable of directly driving a termi-
nated SCSI bus for a compact imple-
mentation.
FEATURES
u
Asynchronous Transfer Rate Up to
4 Mbytes/sec
u
Low Power CMOS Technology
u
Replaces NCR 5380/53C80/
53C80-40 and AMD Am5380/
53C80
u
On-Chip SCSI Bus Drivers
u
Supports Arbitration, Selection/
Reselection, Initiator or Target Roles
u
Programmed or DMA I/O, Hand-
shake or Wait State DMA Interlock
u
DECC SMD No.
5962-90548 — L53C80
u
Package Styles Available:
• 40/48-pin Plastic DIP
• 48-pin Sidebraze, Hermetic DIP
• 44-pin Plastic LCC, J-Lead
L5380/53C80 B
LOCK
D
IAGRAM
CPU DATA BUS
D
7-0
MODE
REGISTER
CS
IOR
IOW
A
2
A
1
A
0
RESET
IRQ
ID SELECT
REG
CURRENT SCSI
DATA BUS REG
SCSI INPUT
DATA REG
SCSI OUTPUT
DATA REG
CPU
I/F
LOGIC
CONTROL
LOGIC
ID
COMPARE
PARITY
GEN/CHECK
DMA STATUS
REG
SCSI DATA BUS
SDBP
SDB
7-0
SDBP
ARBITRATION
LOGIC
DRQ
DACK
EOP
READY
TARGET
COMMAND
REG
EN SCSI BUS,
TEST MODE 2
INITIATOR
COMMAND
REG
CURRENT SCSI
CONTROL REG
3
RST, BSY
SEL, ACK
ATN
I/O, REQ
C/D, MSG
DMA
I/F
LOGIC
REQ/ACK
HANDSHAKE
LOGIC
SCSI PHASE
COMPARE
CONTROL AND STATUS BUS
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L5380/53C80
DEVICES INCORPORATED
SCSI Bus Controller
shake between the initiator and target.
Data is latched by the target on the
lowgoing edge of ACK for target
receive operations.
ATN — ATTENTION
Bidirectional/Active low. ATN is
asserted by the initiator after success-
ful selection of a target, to indicate an
intention to send a message to the tar-
get. The target responds to ATN by
entering the MESSAGE OUT phase.
RST — SCSI BUS RESET
Bidirectional/Active low. RST when
active indicates a SCSI bus reset
condition.
I/O — INPUT/OUTPUT
Bidirectional/Active low. I/O is
controlled by the target and specifies
the direction of information transfer.
When I/O is asserted, the direction of
transfer is to the initiator. I/O is also
asserted by the target during RESE-
LECTION phase to distinguish it from
SELECTION phase.
C/D — CONTROL/DATA
B. Microprocessor Bus
CS — CHIP SELECT
Input/Active low. This signal enables
reading or writing of the internal
registers by the microprocessor, using
memory mapped I/O. An alternate
method for reading selected registers
is available for DMA.
DRQ — DMA REQUEST
Output/Active high. This signal is
used to indicate that the L5380/53C80
is ready to execute the next cycle of a
DMA transfer on the microprocessor
bus. For send operations, it indicates
that the output data register is ready
to receive the next byte from the DMA
controller or CPU. For receive opera-
tions, it indicates that the input data
register contains the next byte to be
read by the DMA controller or CPU.
IRQ — INTERRUPT REQUEST
Output/Active high. The L5380/
53C80 asserts this signal to indicate to
the microprocessor that one of the
several interrupt conditions have been
met. These include SCSI bus fault
conditions as well as other events
requiring microprocessor intervention.
Most interrupt types are individually
maskable.
IOR — I/O READ
Input/Active low. IOR is used in con-
junction with CS and A
2–0
to execute a
memory mapped read of a L5380/
53C80 internal register. It is also used
in conjunction with DACK to execute
a DMA read of the SCSI Input Data
Register.
READY — READY
Output/Active high. Ready is used
rather than DRQ as an alternate
method for controlling DMA data
transfer. This DMA type is termed
blockmode DMA and must be specifi-
cally enabled by the CPU. In block-
PIN DEFINITIONS
A. SCSI Bus
SDB
7–0
— SCSI DATA BUS 7–0
Bidirectional/Active low. The 8-bit
SCSI data bus is defined by these pins.
SDB
7
is the most significant bit.
During arbitration phase, these lines
contain the SCSI ID numbers of all
initiators arbitrating for the SCSI bus;
SDB
7
represents the initiator with the
highest priority. During the selec-
tion/reselection phase, these lines
contain the ID number of the device
that won the arbitration along with
the ID number of the device to be
selected/reselected.
SDBP — SCSI DATA BUS PARITY
Bidirectional/Active low. SDBP is the
parity bit of the SCSI data bus. Odd
parity is used, meaning that the total
number of ones on the bus, including
the parity bit, is odd. Parity is always
generated when sending information,
however checking for parity errors
when receiving information is a user
option. Parity is not valid during
arbitration phase.
SEL — SELECT
Bidirectional/Active low. SEL is
asserted by the initiator to select a
target. It is also asserted by the target
when reselecting it as an initiator.
BSY — BUSY
Bidirectional/Active low. BSY is
asserted to indicate that the SCSI bus
is active.
ACK — ACKNOWLEDGE
Bidirectional/Active low. ACK is
asserted by the initiator during any
information transfer phase in response
to assertion of REQ by the target.
Similarly, ACK is deasserted after
REQ becomes inactive. These two
signals form the data transfer hand-
Bidirectional/Active low. C/D is
controlled by the target and when
asserted, indicates CONTROL (com-
mand or status) information is on the
SCSI data bus. DATA is specified
when C/D is deasserted.
MSG — MESSAGE
Bidirectional/Active low. MSG is
controlled by the target, and when
asserted indicates MESSAGE phase.
REQ — REQUEST
Bidirectional/Active low. REQ is
asserted by the target to begin the
handshake associated with transfer of
a byte over the SCSI data bus. REQ is
deasserted upon receipt of ACK from
the initiator. Data is latched by the
initiator on the lowgoing edge of REQ
for initiator receive operations.
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DEVICES INCORPORATED
SCSI Bus Controller
A
2-0
— ADDRESS 2-0
Inputs/Active high. These signals, in
conjunction with CS, IOR, and IOW,
address the L5380/53C80 internal
registers for CPU read/write opera-
tions.
D
7–0
— DATA 7–0
Bidirectional/Active high. These
signals are the microprocessor data
bus. D
7
is the most significant bit.
L5380/53C80
INTERNAL REGISTERS
Overview
The L5380/53C80 contains registers
that are directly addressed by the
microprocessor. These registers allow
for monitoring of SCSI bus activity,
controlling the operation of the
L5380/53C80, and determining the
cause of interrupts. In many cases, a
read-only and a write-only register are
mapped to the same address. Some
addresses are dummy registers which
are used to implement a control
operation but do not correspond to a
physical register. The state of the CPU
data bus when writing or reading
these dummy registers is ‘don’t care’.
Tables 1 and 3 show the address and
name of each register as well as bit
definitions.
Register Descriptions
A. Write Operations
The following paragraphs give
detailed descriptions of the function of
each bit in the L5380/53C80 internal
registers for write operations as
shown in Table 1.
WRITE ADDRESS 0
Output Data Register
The Output Data Register is a write-
only register used for sending infor-
mation to the SCSI data bus. During
arbitration, the arbitrating SCSI device
asserts its ID via this register. The
device which wins arbitration also
asserts the “OR” of its ID and the ID
of the target/initiator to be selected/
reselected. In programmed I/O mode
this register is written using CS and
IOW with A
2–0
= 000. In DMA mode,
it is written when IOW and DACK are
simultaneously active, irrespective of
the state of the address lines. Note
that a “1” written to the Output Data
Register becomes a low state when
asserted on the active-low SCSI bus.
WRITE ADDRESS 1
Initiator Command Register
The Initiator Command Register is a
read/write register which allows CPU
control of the SCSI signals asserted by
the initiator. Some bits in this register
are not readable, and these positions
are mapped to status bits useful in
monitoring the progress of arbitration.
These, along with the initiation of
system-wide reset and test functions,
may also be of use to the target.
R1 Bit 7 — Assert RST
When this bit is set, the L5380/53C80
asserts the RST line on the SCSI bus,
initializing all devices on the bus to
the reset condition. All logic and
internal registers of the L5380/53C80
are reset, except for the Assert RST bit
itself, the Testmode bit (R1 bit 6) and
the IRQ (interrupt request) latch. The
IRQ pin becomes active indicating a
SCSI bus reset interrupt. This inter-
rupt is not maskable.
R1 Bit 6 — Testmode
When this bit is set, the L5380/53C80
places all outputs, including both SCSI
and CPU signals, in a high impedance
state. This effectively removes the
device from the system as an aid to
system diagnostics. Note that internal
registers may still be written to while
in Testmode. The L5380/53C80
returns to normal operation when
Testmode is reset. The Testmode bit is
reset by either writing a “0” to R1 bit 6
mode DMA, data is throttled by treat-
ing the L5380/53C80 as wait state
memory. I/O (DMA) cycles are
initiated at the maximum rate sustain-
able by the DMA controller/memory
subsystem, but all cycles are extended
(wait-states inserted) until READY is
asserted by the L5380/53C80. This is
generally the fastest DMA method
since memory subsystem addressing
can be overlapped with SCSI opera-
tions (flyby mode).
DACK — DMA ACKNOWLEDGE
Input/Active low. DACK is used in
conjunction with IOR or IOW to
enable reading or writing of the SCSI
Input and Output Data Registers
when in DMA mode. DACK resets
DRQ and must not occur simultane-
ously with CS.
EOP — END OF PROCESS
Input/Active low. This input is used
to indicate to the L5380/53C80 that a
DMA transfer is to be concluded. The
L5380/53C80 can automatically
generate an interrupt in response to
receiving EOP from the DMA control-
ler.
RESET — CPU BUS RESET
Input/Active low. This input clears
all internal registers and state machines.
It does not result in assertion of the
RST signal on the SCSI bus and
therefore affects only the local L5380/
53C80 and not other devices on the
bus.
IOW — I/O WRITE
Input/Active low. IOW is used in
conjunction with CS and A
2–0
to
execute a memory mapped write of a
L5380/53C80 internal register. It is
also used in conjunction with DACK
to execute a DMA write of the SCSI
Output Data Register.
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DEVICES INCORPORATED
SCSI Bus Controller
transfer) and no phase mismatch
condition can exist. A phase mis-
match occurs when the MSG, C/D,
and I/O bits of the Target Command
Register (R3) do not match the corre-
sponding SCSI control lines.
When the L5380/L53C80 is operating
as a target, the Targetmode bit will be
set, and in this case Assert Data Bus
will enable the outputs uncondition-
ally.
The Assert Data Bus bit need not be
set for arbitration to occur; when the
Arbitrate bit (R2 bit 0) is set, and a bus
free condition is detected, the data bus
will be enabled for arbitration regard-
less of the state of the Assert Data Bus
bit.
Finally, note that the Testmode bit
(R1 bit 6) overrides all other controls,
including Assert Data Bus and Arbi-
trate, and disables all outputs.
WRITE ADDRESS 2
Mode Register
The Mode register is a read/write
register which provides control over
several aspects of L5380/53C80
operation. Programmed I/O or two
different types of DMA transfer may
be selected, initiator or target device
operation is accommodated, and
parity checking and interrupts may be
enabled via this register. The function
of each individual bit is described as
follows:
R2 Bit 7 — Blockmode
This bit must be used in conjunction
with DMA Mode (R2 bit 1). It is used
to select the type of handshake
desired between the L5380/53C80 and
the external DMA controller. See
“L5380/53C80 Data Transfers” for a
complete discussion of the transfer
types supported.
R2 Bit 6 — Targetmode
When this bit is set, the L5380/53C80
will operate as a SCSI target device.
This enables the SCSI signals I/O,
C/D, MSG, and REQ to be asserted.
When Targetmode is reset, the device
will operate as an initiator. This
enables the SCSI signals ATN and
ACK to be asserted. Targetmode also
affects state machine operation for
DMA transfers and the conditions
necessary for enabling the SCSI Data
bus drivers. (See Assert Databus,
R1 bit 0).
R2 Bit 5 — Enable Parity Check
When this bit is set, information
received on the SCSI data bus is
checked for odd parity. The Parity
Error latch will be set whenever data
is received under DMA control or the
Current SCSI Data Register (Read
Register 0) is read by the CPU. The
state of the Parity Error latch can be
determined by reading R5 bit 5, and it
can be reset by a read to Address 7.
Note that ENABLE PARITY CHECK
must be set if parity error interrupts
are to be generated. This interrupt can
be separately masked by the Enable
Parity Interrupt bit (R2 bit 4) while
retaining the state of the Parity Error
latch for later examination by the
CPU.
R2 Bit 4 — Enable Parity Interrupt
When this bit is set, the L5380/53C80
will set the interrupt request latch,
and assert IRQ (interrupt request) if it
detects a parity error. Enable Parity
Check (R2 bit 5) must also be set if
parity error interrupts are desired.
R2 Bit 3 — Enable End Of DMA
Interrupt
When this bit is set, the L5380/53C80
will set the interrupt request latch,
and assert IRQ (interrupt request) if it
detects a valid EOP (End of Process)
signal. EOP is normally generated by
a DMA controller to indicate the end
of a DMA transfer. EOP is valid only
when coincident with IOR or IOW and
DACK.
or via the RESET (CPU reset) pin.
Testmode is not affected by the RST
(SCSI bus reset) signal, or by the
Assert RST bit in the Initiator Com-
mand Register (R1 bit 7).
R1 Bit 5 — Not Used
R1 Bit 4 — Assert ACK
When this bit is set, ACK is asserted
on the SCSI bus. Resetting this bit
deasserts ACK. Note that ACK will
be asserted only if the Targetmode bit
(R2 bit 6) is reset, indicating that the
L5380/53C80 is acting as an initiator.
R1 Bit 3 — Assert BSY
When this bit is set, BSY is asserted on
the SCSI bus. Resetting this bit deas-
serts BSY. BSY is asserted to indicate
that the device has been selected or
reselected, and deasserting BSY causes
a bus free condition.
R1 Bit 2 — Assert SEL
When this bit is set, SEL is asserted on
the SCSI bus. Resetting this bit deas-
serts SEL. SEL is normally asserted
after a successful arbitration.
R1 Bit 1 — Assert ATN
When this bit is set, ATN is asserted
on the SCSI bus. Resetting this bit
deasserts ATN. ATN is asserted by
the initiator to request message out
phase. Note that ATN will be asserted
only if the Targetmode bit (R2 bit 6) is
reset, indicating that the L5380/53C80
is acting as an initiator.
R1 Bit 0 — Assert Data Bus
When this bit is set, the open drain
SCSI data bus and parity drivers are
enabled and the contents of the
Output Data Register are driven onto
the SCSI data lines. In addition to the
Assert Data Bus bit, enabling of the
SCSI bus drivers requires one of the
following two sets of conditions:
When the L5380/53C80 is operating
as an initiator, the Targetmode bit
(R2 bit 6) must be reset, the I/O pin
must be negated (initiator to target
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DEVICES INCORPORATED
SCSI Bus Controller
T
ABLE
1.
W
RITE
R
EGISTERS
3
SDB
3
2
SDB
2
1
SDB
1
0
SDB
0
R2 Bit 2 — Monitor Busy
When this bit is set, the L5380/53C80
continuously monitors the state of the
BSY signal. Absence of BSY for a
period longer than 400 ns (but less than
1200 ns) will cause the L5380/53C80 to
set the BSYERR and IRQ (interrupt
request) latches. In addition, the six
least significant bits of the Initiator
Command Register are reset, and all
SCSI data and control outputs are
disabled until the BSYERR latch is reset.
This effectively disconnects the L5380/
53C80 from the SCSI bus in response to
an unexpected disconnect by another
device. It also allows the CPU to be
interrupted when the SCSI bus becomes
free in systems where arbitration is not
used and an EOP signal is not available.
R2 Bit 1 — DMA Mode
When this bit is set, the L5380/53C80’s
internal state machines automatically
control the SCSI signals REQ and ACK
(as appropriate for initiator or target
operation) and the CPU signals DRQ
and READY. DMA Mode must be set
prior to starting a DMA transfer in
either direction. The DMA Mode bit is
reset whenever a bus free condition is
detected (BSY is not active). This aborts
DMA operations when a loss of BSY
occurs, regardless of the state of the
Monitor Busy bit (R2 bit 2.) The DMA
Mode bit is not reset when EOP is
received, but must be specifically reset
by the CPU. EOP does, however,
inhibit additional DMA cycles from
occurring.
R2 Bit 0 — Arbitrate
This bit is set to indicate a desire to
arbitrate for use of the SCSI bus. Before
setting the Arbitrate bit, the SCSI
Output Data Register (Write Register 0)
must be written with the SCSI ID
assigned to the arbitrating SCSI device.
The bit position of register R0 which is
set represents the priority number of
the SCSI device, with bit 7 the highest
priority. See the section on “Arbitra-
tion” for a full discussion of the L5380/
53C80 arbitration procedure.
Address 0 — Output Data Register
7
6
5
4
SDB
7
SDB
6
SDB
5
SDB
4
Address 1 — Initiator Command Register
7
6
5
4
3
ASSERT
RST
TEST
MODE
2
1
0
ASSERT ASSERT ASSERT ASSERT ASSERT
ACK
BSY
SEL
ATN
DATA
BUS
Address 2 — Mode Register
7
6
5
4
3
2
MONI-
TOR
BUSY
1
DMA
MODE
0
ARBI-
TRATE
BLOCK TARGET ENABLE ENABLE ENABLE
MODE
MODE PARITY PARITY EODMA
CHECK INT'RPT INT'RPT
Address 3 — Target Command Register
7
LAST
BYTE
SENT
6
5
4
3
2
1
0
ASSERT ASSERT ASSERT ASSERT
REQ
MSG
C/D
I/O
Address 4 — ID Select Register
7
6
5
4
SDB
7
SDB
6
SDB
5
SDB
4
3
SDB
3
2
SDB
2
1
SDB
1
0
SDB
0
Address 5 — Start DMA Send
7
6
5
4
3
2
1
0
Address 6 — Start DMA Target Receive
7
6
5
4
3
2
1
0
Address 7 — Start DMA Initiator Receive
7
6
5
4
3
2
1
0
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