MC14598BDW datasheet, PDF - EEWORLD Datasheet

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MC14598BDW: DescriptionD Latch, 4000/14000/40000 Series, 1-Func, High Level Triggered, 1-Bit, True Output, CMOS, PDSO16, SOIC-16; Categorylogic logic; File Size262KB，9 Pages; ManufacturerMotorola ( NXP ); Websitehttps://www.nxp.com

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MC14598BDW Overview

D Latch, 4000/14000/40000 Series, 1-Func, High Level Triggered, 1-Bit, True Output, CMOS, PDSO16, SOIC-16

MC14598BDW Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Motorola ( NXP )
package instruction	SOP, SOP18,.4
Reach Compliance Code	unknown
Other features	1:8 DMUX FOLLOWED BY LATCH
series	4000/14000/40000
JESD-30 code	R-PDSO-G16
JESD-609 code	e0
length	10.3 mm
Load capacitance (CL)	50 pF
Logic integrated circuit type	D LATCH
MaximumI(ol)	0.0012 A
Number of digits	1
Number of functions	1
Number of terminals	16
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Output characteristics	3-STATE
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP18,.4
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5/15 V
Prop。Delay @ Nom-Sup	160 ns
propagation delay (tpd)	320 ns
Certification status	Not Qualified
Maximum seat height	2.65 mm
Maximum supply voltage (Vsup)	18 V
Minimum supply voltage (Vsup)	3 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
Trigger type	HIGH LEVEL
width	7.5 mm

MC14598BDW Preview

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

MC14599

See Page 6-174

8-Bit Bus-Compatible Latches

The MC14597B and MC14598B are 8–bit latches, one addressed with an

internal counter and the other addressed with an external binary address.

The 8 latch–outputs are high drive, three–state and bus line compatible. The

drive capability allows direct applications with MPU systems such as the

Motorola 6800 family.

With MC14597B, a 3–bit address counter (clocked on the falling edge of

Increment) selects the appropriate latch. The latches of the MC14598B are

accessed via the Address pins, A0, A1, and A2. A Full Flag is provided on

the MC14597B to indicate the position of the Address counter.

All 8 outputs from the latches are available in parallel when Enable is in the

low state. Data is entered into a selected latch from the Data pin when the

Strobe is high. Master reset is available on both parts.

•

Serial Data Input

•

Three–State Bus Compatible Parallel Outputs

•

Three–State Control Pin (Enable) TTL Compatible Input

•

Open Drain Full Flag (Multiple Latch Wire–O Ring)

•

Master Reset

•

Level Shifting Inputs on All Except Enable

•

Diode Protection — All Inputs

•

Supply Voltage Range — 3.0 Vdc to 18 Vdc

•

Capable of Driving TTL Over Rated Temperature Range

With Fanout as Follows:

1 TTL Load

4 LSTTL Loads

BLOCK DIAGRAMS

RESET

LOGIC

4 ENABLE

MC14597B

MC14598B

L SUFFIX

CERAMIC

CASE 620

P SUFFIX

PLASTIC

CASE 648

D SUFFIX

SOIC

CASE 751B

ORDERING INFORMATION

MC14597BCP

MC14597BCL

MC14597BDW

Plastic

Ceramic

SOIC

TA = – 55° to 125°C for all packages.

L SUFFIX

CERAMIC

CASE 726

MC14597B

RESET

LATCHES

THREE

STATE

OUTPUT

BUFFERS

VDD

RESET

P SUFFIX

PLASTIC

CASE 707

DATA

STROBE

3–BIT

ADDRESS

COUNTER

INCREMENT

VDD = 16

VSS = 8

FULL

LOGIC

FULL

ADDRESS

DECODER

DATA

ENABLE

FULL

STROBE

INCREMENT

VSS

ORDERING INFORMATION

MC14598BCP

MC14598BCL

Plastic

Ceramic

TA = – 55° to 125°C for all packages.

VDD

MC14598B

ENABLE

RESET

DATA

STROBE

A0 7

A1 8 ADDRESS

A2 10 DECODER

VDD = 18

VSS = 9

LATCHES

THREE

STATE

OUTPUT

BUFFERS

OUTPUT

TRUTH TABLE

Enable

Outputs

High Impedance

DATA

ENABLE

STROBE

VSS

Dn = State of nth latch

NC = NO CONNECTION

REV 3

1/94

MOTOROLA CMOS LOGIC DATA

Motorola, Inc. 1995

MC14597B MC14598B

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

MAXIMUM RATINGS*

(Voltages Referenced to VSS)

Symbol

VDD

Vin

Vout

Iin, lout

Tstg

Parameter

DC Supply Voltage

Value

Unit

– 0.5 to + 18.0

Input Voltage, Enable (DC or Transient)

Input Voltage, All other Inputs

(DC or Transient)

Output Voltage (DC or Transient)

Input or Output Current (DC or Transient),

per Pin

Power Dissipation, per Package†

Storage Temperature

Lead Temperature (8–Second Soldering)

– 0.5 to VDD + 0.5

– 0.5 to VDD + 12

– 0.5 to VDD + 0.5

500

– 65 to + 150

260

This device contains protection circuitry to

guard against damage due to high static

voltages or electric fields. However, pre-

cautions must be taken to avoid applications of

any voltage higher than maximum rated volt-

ages to this high–impedance circuit. For proper

operation, Vin and Vout should be constrained

to the range VSS

(Vin or Vout)

VDD.

Unused inputs must always be tied to an

appropriate logic voltage level (e.g., either VSS

or VDD). Unused outputs must be left open.

* Maximum Ratings are those values beyond which damage to the device may occur.

†Temperature Derating:

“P and D/DW” Packages: – 7.0 mW/C From 65

C To 125

C Ceramic

“L” Packages: – 12 mW/

C From 100

C To 125

ELECTRICAL CHARACTERISTICS

(Voltages Referenced to VSS)

Characteristic

Symbol

VOL

VDD

Vdc

5.0

Min

—

– 55

125

Max

Min

—

Typ #

Max

Min

—

Max

Unit

Vdc

Output Voltage

Vin = VDD or 0

“0” Level

0.05

—

0.8

1.6

2.4

—

0.05

—

0.8

1.6

2.4

—

0.05

—

0.8

1.6

2.4

“1” Level

Vin = 0 or VDD

Input Voltage** — Enable “0” Level

(VO = 4.5 or 0.5 Vdc)

(VO = 9.0 or 1.0 Vdc)

(VO = 13.5 or 1.5 Vdc)

“1” Level

(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)

(VO = 1.5 or 13.5 Vdc)

Input Voltage

“0” Level

Other Inputs

(VO = 4.5 or 0.5 Vdc)

(VO = 9.0 or 1.0 Vdc)

(VO = 13.5 or 1.5 Vdc)

(VO = 0.5 or 4.5 Vdc) “1” Level

(VO = 1.0 or 9.0 Vdc)

(VO = 1.5 or 13.5 Vdc)

Output Drive Current

Source

(Full — Sink Only)

(VOH = 4.6 Vdc)

(VOH = 9.5 Vdc)

(VOH = 13.5 Vdc)

(VOL = 0.4 Vdc)

(VOL = 0.5 Vdc)

(VOL = 1.5 Vdc)

Input Current

Three–State Leakage Current

Input Capacitance (Vin = 0)

Quiescent Current

(Per Package)

**Total Supply Current at an

**External

Load Capacitance of

**130

Sink

VOH

4.95

9.95

14.95

—

2.0

6.0

4.95

9.95

14.95

—

2.0

6.0

5.0

1.1

2.2

3.4

1.9

3.1

4.3

4.95

9.95

14.95

—

2.0

6.0

Vdc

VIL

Vdc

VIH

Vdc

—

Vdc

5.0

—

3.5

7.0

1.5

3.0

4.0

—

3.5

7.0

2.25

4.50

6.75

2.75

5.50

8.25

1.5

3.0

4.0

—

3.5

7.0

1.5

3.0

4.0

—

Vdc

VIL

VIH

5.0

IOH

5.0

IOL

5.0

—

5.0

– 1.0

—

1.6

—

–

—

0.1

—

5.0

– 1.0

—

1.6

—

– 2.0

– 6.0

– 12

3.2

6.0

0.00001

5.0

0.005

0.010

0.015

—

0.1

7.5

5.0

– 1.0

—

1.6

—

1.0

3.0

—

150

300

600

mAdc

Iin

ITL

Cin

IDD

µAdc

IT = (2.0

µA/kHz)

f + IDD

IT = (4.0

µA/kHz)

f + IDD

IT = (6.0

µA/kHz)

f + IDD

†Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

** The formulas given are for the typical characteristics only at 25

µAdc

MC14597B MC14598B

MOTOROLA CMOS LOGIC DATA

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

SWITCHING CHARACTERISTICS*

(TA = 25

C, CL = 130 pF + 1 TTL Load)

Characteristic

Symbol

tTLH,

tTHL

VDD

Vdc

5.0

tWH,

tWL

5.0

tsu

5.0

trem

5.0

100

– 25

– 15

– 10

—

100

200

100

400

200

170

100

200

100

—

All Types

Typ #

100

160

125

100

200

100

200

100

175

160

120

100

150

Min

—

320

240

160

200

100

200

100

300

160

100

Max

200

100

320

250

200

400

200

160

400

200

160

350

180

140

—

Unit

Output Rise and Fall Time

tTLH, tTHL = (0.5 ns/pF) CL + 35 ns

tTLH, tTHL = (0.2 ns/pF) CL + 25 ns

tTLH, tTHL = (0.16 ns/pF) CL + 20 ns

Propagation Delay Time

Enable to Output

tPLH,

tPHL

Strobe to Output

Strobe to Full (MC14597B only)

Reset to Output

Pulse Width

Enable

Strobe

Increment (MC14597B only)

Reset

Setup Time

Data

Address (MC14598B only)

Increment (MC14597B only)

Hold Time

Data

Address (MC14598B only)

Reset Removal Time

* The formulas given are for the typical characteristics only at 25

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

MOTOROLA CMOS LOGIC DATA

MC14597B MC14598B

MC14597B FUNCTION DIAGRAM

VDD

ENABLE 4

TO OTHER

LATCHES

VDD

D Q

CLK

STROBE 6

VDD

5 FULL

RESET 2

DATA 3

1 D0

TO OTHER

LATCHES

SEVEN

SELECT

3 STAGE COUNTER

AND DECODER

CLK

INCREMENT 7

ZERO

SELECT

ONE LATCH

VSS

ADDITIONAL 7 LATCHES

MC14597B TIMING DIAGRAMS

D6 (INTERNAL)

D7 (INTERNAL)

tWL

INCREMENT

DATA

STROBE

FULL

trem

50%

tTLH

tPHL

FULL

10%

90%

tTHL

10%

20 ns

90%

tsu

10%

20 ns

90%

tPHL

tsu

10%

tWH

RESET

NOTE: Enable in High state.

ENABLE

tWL

* 1.4 V with VDD = 5.0 V

NOTES:

1. High–impedance output state (another device controls bus).

2. Reset in High state.

MC14597B MC14598B

MOTOROLA CMOS LOGIC DATA

MC14598B FUNCTION DIAGRAM

RESET 2

VDD

DATA 3

TO OTHER

LATCHES

STROBE 6

1 D0

ENABLE 4

EACH LATCH

TO OTHER

LATCHES

A0 7

A1 8

A2 10

(M.S.B)

ADDRESS

DECODER

ADDITIONAL 7 LATCHES

ZERO

SELECT

VSS

MC14598B TIMING DIAGRAM

90%

10%

tTHL

tPLH

RESET

A0, A1, A2

50%

tPHL

tTLH

20 ns

50%

tsu th

DATA

STROBE

ENABLE

* 1.4 V with VDD = 5.0 V

NOTES:

1. High–impedance output state (another device controls bus).

2. Output Load as for MC14597B.

90%

10%

20 ns

tsu

50%

90%

10%

20 ns

90%

10%

tPLH

90%

10%

50%

MOTOROLA CMOS LOGIC DATA

MC14597B MC14598B

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