LSI/CSI
UL
®
LS7055
LS7056
(631) 271-0400 FAX (631) 271-0405
January 2003
LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747
A3800
6 DECADE PREDETERMINING UP/DOWN COUNTER
FEATURES:
• +4.75V to +15V (Vss - V
DD
)
• Preset, Presignal and Mainsignal Store
• DC to 250kHz Count Frequency
• Fully Synchronous Operation
Three Comparators with Output Flags
Automatic or Manual Preset/Reset Control
• Thumbwheel Interface for Storage Selects
• Prescale on Count Input Selectable
• Count Inhibit
• Up/Down Control
• Scan Rate up to 150kHz
• Scan Oscillator has Override Capability
• Blanking Override for Decimal Point Operaton
• Multiplexed 7 Segment and BCD Data Output
• Output latches
• Reset
• Hysteresis on Count Input
• CMOS Type Noise Immunity on all other inputs
• LS7055, LS7056 (DIP) - See Figure 1
DESCRIPTION:
The LS7055/LS7056 is a MOS synchronous 6 decade Up/Down
counter. The circuit includes storages and comparators, zero de-
tect, automatic presetting and resetting, output latches, multi-
plexed output BCD and seven segment data. Thumbwheel
switches can be used to provide BCD data to the storage net-
works in the circuit.
COUNT
(Pin 40)
Counter operates at speeds up to 250kHz and advances on the
positive edge of the input count pulse.
UP/DOWN
(Pin 39)
Counter operates in up or down mode. A high input causes the
counter to operate in the up mode while a low input causes it to
operate in the down mode.
COUNT INHIBIT
(Pin 1)
A high input inhibits counting and the counter remains at its last
count. A low input enables counting.
DATA TRANSFER INPUT
(Pin 37)
A high input allows the seven segment display and BCD data to
follow the count (the internal latches become transparent). A low
input prevents updating of the latches as the count advances and
the seven segment display and BCD data outputs remain fixed.
RESET
(Pin 4)
A high input resets and holds all counter stages at zero. A low
input allows counter operation.
PIN ASSIGNMENT - TOP VIEW
COUNT INHIBIT INPUT
DIVIDE CONTROL INPUT 1
DIVIDE CONTROL INPUT 2
RESET INPUT
1
2
3
4
40
39
38
37
36
35
34
33
LSI
COUNT INPUT
UP/DOWN INPUT
ZERO DETECT OUTPUT
DATA TRANSFER INPUT
PRESIGNAL OUTPUT
B1
B2
B4
B8
BLANKING OVERRIDE
g
f
e
d
c
b
a
SCAN OSCILLATOR INPUT
MSD
LSD+4
DIGIT
SELECT
OUTPUTS
SEGMENT
OUTPUTS
BCD
DATA
OUTPUTS
INHIBIT INTERNAL RESET INPUT 5
INHIBIT INTERNAL PRESET INPUT 6
PRESET INPUT
V
DD
(-V)
MAIN SIGNAL OUTPUT
7
8
9
LS7055
32
31
30
29
28
27
26
25
24
23
22
21
B1 10
BCD
DATA
INPUTS
B4 11
B2 12
B8 13
V
SS
(+V)
14
*
SELECT STORAGE INPUT 1 15
SELECT STORAGE INPUT 2 16
LSD 17
DIGIT
SELECT
OUTPUTS
L S D + 1 18
L S D + 2 19
L S D + 3 20
FIGURE 1
*
OPTIONAL CHOICE-LAMP TEST (SPECIFY LS7056)
INHIBIT INTERNAL RESET
(Pin 5)
A high input prevents the automatic reset of the counter to zero when
in the up mode and when the counter reaches the number in the
main signal store.
PRESET
(Pin 7)
A high level presets the BCD counter to the number set in the preset
store. A low input allows counter operation.
INHIBIT INTERNAL PRESET
(Pin 6)
A high input prevents the automatic preset of the counter to the
number set in preset store when in the down mode and the counter
reaches zero.
SELECT STORAGE OF DATA INPUTS
(Pins 15, 16)
Two inputs which allow BCD data to be stored in either the preset,
presignal or main signal store. The proper method for loading the
stores is depicted in Figure 4.
PIN 15
0
1
0
1
PIN16
0
0
1
1
STORAGE
No Selection
Presignal
Main Signal
Preset
7055-012703-1
BCD DATA INPUTS
(Pins 10, 11, 12, 13)
Four inputs containing BCD data which are applied to either the
preset, presignal or main signal stores one decade at a time. This
data can be provided by a set of thumbwheel switches which are
driven by the digit select outputs. Referring to Figure 4, the BCD
data inputs have built in pull down resistors (typically 51k Ohms).
DIVIDE CONTROL
(Pin 2, Pin 3)
Two inputs for selection to divide the count input by either 5, 6 or 1.
PIN 2
0
1
1
PIN 3
0
0
1
LAMP TEST
(LS7056 only) (Pin 31)
A high input will cause the seven segment outputs to provide all 8's
to a display (BCD outputs are not affected).
ZERO DETECT OUTPUT
(Pin 38)
A high output occurs whenever the counter is at zero. In the auto-
matic mode and with the Up/Down input in the down mode, the
counter presets to the number in the preset store and the zero
detect output is typically a 1.5 µs pulse. In the manual mode
(inhibit internal preset is high), the counter remains at zero until a
preset or a count input pulse is applied.
DIGIT SELECT OUTPUTS
(Pins 17, 18, 19, 20, 21, 22)
Six positive outputs for digit identification. The outputs occur
sequentially going from MSD to LSD and can be applied directly to
thumbwheel switches. They must be buffered before being applied
to the seven segment displays either by a CMOS or transistor buf-
fer as shown in Figure 5. Figure 3 indicates the timing relationship
between the digit select outputs and the BCD data outputs.
SEVEN SEGMENT OUTPUTS
(Pins 24, 25, 26, 27, 28, 29, 30)
Capable of sourcing current into the base of a common emitter
NPN transistor for interfacing to a seven segment display. Small
displays needing an average current of 0.5 mA can be interfaced
to the circuit without external transistors. A typcial example of a
12V circuit is shown in Figure 5.
BCD OUTPUTS
(Pins 32, 33, 34, 35)
Four outputs corresponding to the BCD data stored in the latches.
The outputs can be demultiplexed using the circuitry shown in Fig-
ure 4. As can be seen from the timing diagram of Figure 3, the
BCD data output and seven segment outputs are completely
stable during the positive digit select outputs.
POWER-ON-RESET
An external RC network applied to the reset input as shown in Fig-
ure 4 can be used to reset the counter to zero upon application of
power. The preset input must be held low at this time. The RC time
constant should be larger than the power supply rise time. For ex-
ample, a 100kΩ resistor and a 0.1µF capacitor could be used if the
power supply rise time was 5 ms.
POWER SUPPLIES
The circuit operates over the range of +4.75V to +15V. At +4.75V,
the inputs are TTL and CMOS compatible (external pull-up re-
sistors must be provided on any input which does not pull up to
Vss) when using TTL inputs. At +15V, inputs are CMOS compat-
ible. All outputs are CMOS compatible from +4.75V to +15V.
Divide by 5
Divide by 6
Divide by 1
MAIN SIGNAL OUTPUT
(Pin 9)
An internal comparator provides a high level output when the num-
ber set into the main signal store is reached by the counter. In the
automatic mode and with the Up/Down control in the up position,
the counter is reset to zero and the main signal output is typically a
2.5 µs wide pulse. In the manual mode (inhibit internal reset is high)
the output remains high until the next count input or a reset is ap-
plied.
PRESIGNAL OUTPUT
(Pin 36)
The presignal comparator provides a high level output when the
number set into the presignal storage is reached. The output re-
mains high until the next count input or a reset or preset is applied.
SCAN CLOCK INPUT
(Pin 23)
A DC to 150kHz oscillator input port for driving the internal scan
counter is provided. Up to 150kHz may be used when de-
multiplexilng BCD data using the digit select outputs. The fre-
quency of the oscillator is determined by an external RC network as
shown in Figure 4. Table 1 indicates several frequencies and their
associated RC networks. The oscillator can be overridden using an
external driver. Table 2 indicates the external drive requriements.
When displaying, leading zero blanking and unblanking on LSD is
provided.
BLANKING OVERRIDE
(LS7055 only) (Pin 31)
On circuits with this option, unblanking can be made to occur on
any digit by connecting that digit select output to the unblanking in-
put. Since the input has an internal pull down resistor, it can be left
floating when not in use.
TABLE 1
Typical resistor/capacitor values for the scan oscillator
RESISTOR
12kΩ
100kΩ
1.0MΩ
CAPACITOR
1000pF
1000pF
1000pF
TYPICAL FREQUENCY
100kHz
10kHz
1kHz
TABLE 2
Driver Requirements for Overriding Scan Oscillator Input
Power Supply (V)
5
10
15
7055-012703-2
Sink Current
1.0mA
4.5mA
10.0mA
Source Current
0
0
0
MAXIMUM RATINGS
PARAMETER
Storage Temperature
Operating Temperature
Voltage (any pin to Vss)
SYMBOL
Tstg
T
A
Vmax
VALUE
-65 to +150
-25 to +70
-30 to +0.5
UNITS
°C
°C
V
DYNAMIC ELECTRICAL CHARACTERISTICS
(V
DD
= V
GG
= 0V, Vss = +4.75 to +15V, -25°C
≤
T
A
≤
+70°C
unless otherwise specified.)
PARAMETER
Count Input Frequency
Vss = 4.75V
Vss = 10V
Vss = 15V
Pulse Width
Vss = 4.75V
Vss = 10V
Vss = 15V
Rise Time
Fall Time
Scan Input Frequency
Divide Control
Set-Up Time
Hold Time
Reset Pulse Width
**
Reset
Set Up Time
Hold Time
Inhibit Internal Reset
Set Up Time
Hold Time
*
Preset Pulse Width
**
Preset Enable
Set Up Time
Hold Time
*
Data Transfer Pulse Width
**
Data Transfer
Set Up Time
Hold Time
Up/Down
Set Up Time
Hold Time
Count Inhibit
Set Up Time
Hold Time
Data Outputs (C
L
= 10pF)
Rise Time
Fall Time
Vss = 4.75V
Vss = 10V
Vss = 15V
SYM
Fc
Fc
Fc
Tcw
Tcw
Tcw
Tcr
Tcf
Fsc
Tds
Tdh
Trpw
Trs
Trh
Tis
Tirh
Tppw
Tips
Tiph
Tdtw
Tdts
Tdth
Tuds
Tud
Tcs
Tch
Tdr
Tdf
Tdf
Tdf
MIN
DC
DC
DC
2
2.8
4
-
-
DC
2
8
2
0
6
0
3
2
0
6
2
0
6
0
10
2
10
-
-
-
-
MAX
250
175
125
-
-
-
∞
∞
100
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.0
2.0
3.0
4.0
UNITS
kHz
kHz
kHz
µs
µs
µs
µs
µs
kHz
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
DC ELECTRICAL CHARACTERISTICS
(V
DD
= V
GG
= 0V, Vss = +4.75 to +15V, -25°C
≤
T
A
≤
+70°C unless
otherwise specified.)
PARAMETER
Quescent Supply Current
(All Input Pins Tied to Vss)
(All Output Pins Left Open)
Vss = 4.75V
Vss = 15V
Input Capacitance All Inputs
Hysteresis On Count Input
Noise Immunity All Other Inputs
Output Levels All Outputs
(All Output Pins Left Open)
SYM MIN
-
-
MAX
-
UNITS
-
I
DD
I
DD
Cin
V
NL
V
NH
V
OL
V
OH
-
-
-
30%(Vss - V
DD
)
30%(Vss - V
DD
)
30%(Vss - V
DD
)
-
Vss - 1
20
25
10
-
-
-
0.5
-
mA
mA
pF
V
V
V
V
V
7 Segment Output Current
Source Current
Vss = 4.75V, V
OUT
= 0.7V, 70°C I
SEG
0.3
Vss = 4.75V, V
OUT
= 0.7V, 25°C I
SEG
0.4
Vss = 10V, V
OUT
= 7V, 25°C
I
SEG
2.0
Vss = 15V, V
OUT
= 13V, 70°C
I
SEG
3.0
Note: Limit Segment Source Current to 4.5mA max.
Sink Current (V
OUT
= 0.4V)
Vss = 4.75V, 25°C
Vss = 10V, 25°C
Vss = 15V, 25°C
Vss = 15V, 70°C
-
-
-
-
mA
mA
mA
mA
I
SEG
I
SEG
I
SEG
I
SEG
-21
-17
-15
-10
-
-
-
-
µA
µA
µA
µA
BCD, Zero Detect, Mainsignal and Presignal Output Current
Source Current
Vss = 4.75V, V
OUT
= 4.5V, 70°C Io
H
0.10
Vss = 4.75V, V
OUT
= 4.5V, 25°C Io
H
0.13
Vss = 10V, V
OUT
= 9.0V, 25°C
Io
H
0.7
Vss = 15V, V
OUT
= 13V, 25°C
Io
H
2.5
Note: Limit Segment Source Current to 4.5mA max.
Sink Current (V
OUT
= 0.4V)
Vss = 4.75V, 25°C
Vss = 10V, 25°C
Vss = 15V, 25°C
Vss = 15V, 70°C
-
-
-
-
mA
mA
mA
mA
Io
L
Io
L
Io
L
Io
L
-7.5
-6.0
-5.5
-4.0
-
-
-
-
µA
µA
µA
µA
Digit Select Outputs Guard Band Time
within 7 segment & BCD outputs Tgb
See Figure 3
Main Signal, Presignal, Zero Detect
Outputs delay with respect to positive
edge of Count Input
Tdo
0.5
-
µs
Digit Select Output Current
Source Current
Vss = 4.75V, V
OUT
= 4.5V, 70°C Io
H
Vss = 4.75V, V
OUT
= 4.5V, 25°C Io
H
Vss = 10V, V
OUT
= 9V, 25°C
Io
H
Vss = 15V, V
OUT
= 13.5V, 70°C Io
H
Note: Limit digit select current to 10mA.
Sink Current (V
OUT
= 0.4V)
Vss = 4.75V, 25°C
Vss = 10V, 25°C
Vss = 15V, 25°C
Vss = 15V, 70°C
-
3
µs
0.28
0.35
2.0
7.0
-
-
-
-
mA
mA
mA
mA
Io
L
Io
L
Io
L
Io
L
-15
-12
-11
-
-
-
-
µA
µA
µA
µA
Set-Up and Hold times are defined with respect to positive edge of count
input except where indicated by asterisks.
*
Indicates a hold time which must last for at least one whole count cycle
plus 5µs past the next positive edge of count input.
**
Reset, Preset and Data Transfer Pulse Width is as specified except if
applied when a count input is going positive. In that case the set-up and
hold times govern.
The information included herein is believed to be
accurate and reliable. However, LSI Computer Systems,
Inc. assumes no responsibilities for inaccuracies, nor for
any infringements of patent rights of others which may
result from its use.
7055-012703-3
COUNTER AT
MAINSIGNAL VALUE
MAINSIGNAL OUTPUT
COUNTER AT
PRESET NUMBER
MANUAL
RESET
AUTOMATIC
RESET
COUNTER AT
PRESIGNAL VALUE
PRESIGNAL OUTPUT
MANUAL
PRESET
AUTOMATIC
PRESET
COUNTER AT
PRESIGNAL VALUE
PRESIGNAL OUTPUT
COUNTER AT
ZERO
ZERO DETECT OUTPUT
COUNTER AT
MAINSIGNAL
NUMBER
MAINSIGNAL OUTPUT
FIGURE 2. AUTOMATIC OR MANUAL OPERATION IN UP MODE
COUNTER AT
ZERO
ZERO DETECT OUTPUT
FIGURE 3. AUTOMATIC OR MANUAL OPERATION IN DOWN MODE
COUNT INPUT
UP/DOWN
T
UDH
DIVIDE CONTROL
T
ds
COUNT INHIBIT
T
cs
RESET
T
rpw
INHIBIT
INTERNAL RESET
PRESET ENABLE
T
ppw
INHIBIT
INTERNAL PRESET
MAINSIGNAL, PRESIGNAL,
ZERO DETECT OUTPUT
DATA TRANSFER
INPUT
SCAN CLOCK
INPUT
MSD OUTPUT
T
irh
T
ch
T
dh
T
udh
T
iph
T
do
T
do
T
dth
LSD +4 OUTPUT
7 SEGMENTS
OUTPUTS
BCD OUTPUTS
STORAGE SELECT
INPUTS
T
gb
T
gb
BCD DATA
INPUT
*
*
BCD data input assumed to be applied from a set of thumbwheel switches as shown in Figure 5.
FIGURE 4. TIMING DIAGRAM
7055-012703-4
LED DISPLAY
BUFFER
LATCH ENABLE
BUFFER
LE
EXT.
LATCH
LE
LE
LE
LE
BLANKING OVERRIDE
OR LAMP TEST
DATA TRANSFER INPUT
SCAN INPUT
Vss
LOAD
COMMAND
7 SEGMENT OUTPUTS
6 DIGIT
SELECT
OUTPUT
MAINSIGNAL OUTPUT
PRESIGNAL OUTPUT
ZERO DETECT OUTPUT
LS7055/LS7056
SELECT STORAGE
INPUTS
51K
4 BCD DATA
OUTPUTS
INHIBIT INTERNAL
RESET INPUT
RESET INPUT
Vss
1µF
(typical)
10k
V
DD
INHIBIT INTERNAL
PRESET INPUT
PRESET ENABLE
INPUT
Vss
V
DD
UP/DOWN INPUT
100k
(typical)
DIVIDE CONTROL INPUTS
COUNT INPUT
COUNT INHIBIT
BCD DATA INPUTS
Vss
THUMBWHEEL SWITCHES
FIGURE 5. SYSTEM INTERCONNECTION DIAGRAM
7055-012703-5
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