Z86C96
CPS DC-4049-02
C
USTOMER
P
ROCUREMENT
S
PECIFICATION
Z86C96
CMOS Z8
®
M
ICROCONTROLLER
GENERAL DESCRIPTION
The Z86C96 microcontroller introduces a new level of
sophistication to single-chip architecture. The Z86C96 is a
member of the Z8 single-chip microcontroller family with
256 bytes of general-purpose RAM.
The MCU is housed in 64-pin DIP and 68-pin Leaded Chip-
Carrier packages and is manufactured in CMOS technol-
ogy.
Zilog’s CMOS microcontroller offers fast execution, effi-
cient use of memory, sophisticated interrupts, input/output
bit manipulation capabilities, and easy hardware/software
system expansion along with low cost and low power
consumption.
The Z86C96 architecture is characterized by Zilog’s 8-bit
microcontroller core. The device offers a flexible I/O
scheme, an efficient register and address space structure,
multiplexed capabilities between address/data, I/O, and a
number of ancillary features that are useful in many indus-
trial and advanced consumer applications.
The device applications demand powerful I/O capabilities.
The Z86C96 fulfills this with 52 pins dedicated to input and
output. These lines are grouped into six 8-bit ports and one
4-bit port. The ports are configurable under software
control to provide timing, status signals, serial or parallel
I/O with or without handshake, and an address/data bus
for interfacing external memory.
There are three basic address spaces available to support
this wide range of configuration: program memory, data
memory and 236 general-purpose registers.
To unburden the program from coping with the real-time
problems such as counting/timing and serial data commu-
nication, the Z86C96 offers two on-chip Counter/Timers
with a large number of user selectable modes, and a
Asynchronous Receiver/Transmitter (UART - see block
diagram).
Notes:
All Signals with a preceding front slash, "/", are active Low, e.g.:
B//W (WORD is active Low); /B/W (BYTE is active Low, only).
Power connections follow conventional descriptions below:
Connection
Power
Ground
Circuit
V
CC
GND
Device
V
DD
V
SS
DC-4049-02
(6-8-93)
1
Z86C96
CPS DC-4049-02
GENERAL DESCRIPTION
(Continued)
Output Input
Vcc
GND
XTAL
/AS /DS R//W /RESET
Port 3
Machine Timing and
Instruction Control
UART
ALU
Flags
Counter/
Timers (2)
Register
Pointer
Interrupt
Control
Register File
256 x 8-Bit
Program
Counter
Port 6
Port 5
Port 4
Port 2
4
Port 0
4
Port 1
8
Address/Data or I/O
(Byte Programmable)
I/O
(Bit Programmable)
Address or I/O
(Nibble Programmable)
Z-BUS When Used
As Address/Data Bus
Functional Block Diagram
2
Z86C96
CPS DC-4049-02
PIN DESCRIPTION
P44
VCC
P45
XTAL2
XTAL1
P37
P30
N/C
/RESET
R/W
/DS
P46
P47
AS
P35
N/C
GND
P32
P50
P51
P00
P01
P02
P03
P04
P05
P06
P07
VCC
P52
P53
P54
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P43
P42
P36
P31
P41
P40
P27
P26
P25
P24
P23
P22
P60
P61
P21
P20
GND
P33
P34
P62
P63
P17
P16
P15
P14
P13
P12
P57
P56
P11
P10
P55
Z86C96
DIP
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
64-Pin Dual In-Line Plastic Pin Assignments
3
Z86C96
CPS DC-4049-02
PIN DESCRIPTION
(Continued)
/R
ES
E
P3 T
0
P3
7
XT
AL
1
XT
AL
P4 2
5
VC
C
P4
4
P4
3
P4
2
P3
6
P3
1
P4
1
P4
0
P2
7
3
2
1
9
R/W
/P0DS
/DS
P46
P47
/P1DS
/AS
/DTIMERS
P35
N/C
GND
P32
P50
P51
P00
P01
P02
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
8
7
6
5
4
68 67 66 65 64 63 62 61
60
59
58
57
56
55
54
P24
P23
P22
P60
P61
P21
P20
SCLK
/SYNC
GND
P33
P34
P62
P63
P17
P16
P15
Z86C96
PLCC
P2
6
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
7
VC
C
P5
2
P5
3
P5
4
P0
3
P0
4
P0
5
P0
6
5
P1
0
P1
1
P0
68-Pin Plastic Leaded Chip Carrier Pin Assignments
4
P5
7
P1
2
P1
3
P1
4
P5
P5
6
P2
5
53
52
51
50
49
48
47
46
45
44
Z86C96
CPS DC-4049-02
ABSOLUTE MAXIMUM RATINGS
Symbol Description
V
CC
T
STG
T
A
Supply Voltage*
Storage Temp
Oper Ambient Temp
Min
–0.3
–65
Max
+7.0
+150°
†
Units
V
C
C
Stress greater than those listed under Absolute Maximum
Ratings may cause permanent damage to the device. This
is a stress rating only; operation of the device at any
condition above those indicated in the operational sec-
tions of these specifications is not implied. Exposure to
absolute maximum rating conditions for an extended pe-
riod may affect device reliability.
Notes:
* Voltages on all pins with respect to GND.
† See Ordering Information
STANDARD TEST CONDITIONS
The characteristics listed below apply for standard test
conditions as noted. All voltages are referenced to GND.
Positive current flows into the referenced pin (see Test
Load Diagram).
From Output
Under Test
+5V
2.1 kΩ
150 pF
9.1 kΩ
Test Load Diagram
PLEASE NOTE
This device will not operate in extended Timing mode. Set Register 248 (F8H), D5 = 0.
5
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