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“Standard”:
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DATA SHEET
MOS INTEGRATED CIRCUIT
μ
PD44165084A-A, 44165094A-A, 44165184A-A, 44165364A-A
18M-BIT QDR
TM
II SRAM
4-WORD BURST OPERATION
Description
The
μ
PD44165084A-A is a 2,097,152-word by 8-bit, the
μ
PD44165094A-A is a 2,097,152-word by 9-bit, the
μ
PD44165184A-A is a 1,048,576-word by 18-bit and the
μ
PD44165364A-A is a 524,288-word by 36-bit synchronous quad
data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell.
The
μ
PD44165084A-A,
μ
PD44165094A-A,
μ
PD44165184A-A and
μ
PD44165364A-A integrate unique synchronous
peripheral circuitry and a burst counter. All input registers controlled by an input clock pair (K and K#) are latched on
the positive edge of K and K#.
These products are suitable for application which require synchronous operation, high speed, low voltage, high density
and wide bit configuration.
These products are packaged in 165-pin PLASTIC BGA.
Features
•
1.8 ± 0.1 V power supply
•
165-pin PLASTIC BGA (13 x 15)
•
HSTL interface
•
PLL circuitry for wide output data valid window and future frequency scaling
•
Separate independent read and write data ports with concurrent transactions
•
100% bus utilization DDR READ and WRITE operation
•
Four-tick burst for reduced address frequency
•
Two input clocks (K and K#) for precise DDR timing at clock rising edges only
•
Two output clocks (C and C#) for precise flight time
and clock skew matching-clock and data delivered together to receiving device
•
Internally self-timed write control
•
Clock-stop capability. Normal operation is restored in 1,024 cycles after clock is resumed.
•
User programmable impedance output
•
Fast clock cycle time : 3.3 ns (300 MHz) , 3.7 ns (270 MHz) , 4.0 ns (250 MHz) , 5.0 ns (200 MHz)
•
Simple control logic for easy depth expansion
•
JTAG boundary scan
•
Operating ambient temperature : Commercial T
A
= 0 to +70°C (-E33, -E40, -E50)
Industrial
T
A
= –40 to +85°C (-E37Y, -E40Y, -E50Y)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. M19870EJ1V0DS00 (1st edition)
Date Published July 2009
Printed in Japan
2009
FPGA/CPLD
京公网安备 11010802033920号
EEWORLD
