UPD4481321GF-A75Y datasheet, PDF

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UPD4481321GF-A75Y: DescriptionZBT SRAM, 256KX32, 7.5ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, LQFP-100; Categorystorage storage; File Size337KB，28 Pages; ManufacturerNEC Electronics

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UPD4481321GF-A75Y Overview

ZBT SRAM, 256KX32, 7.5ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, LQFP-100

UPD4481321GF-A75Y Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	NEC Electronics
Parts packaging code	QFP
package instruction	LQFP,
Contacts	100
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Maximum access time	7.5 ns
Other features	FLOW-THROUGH ARCHITECTURE
JESD-30 code	R-PQFP-G100
JESD-609 code	e0
length	20 mm
memory density	8388608 bit
Memory IC Type	ZBT SRAM
memory width	32
Number of functions	1
Number of terminals	100
word count	262144 words
character code	256000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	256KX32
Package body material	PLASTIC/EPOXY
encapsulated code	LQFP
Package shape	RECTANGULAR
Package form	FLATPACK, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum seat height	1.7 mm
Maximum supply voltage (Vsup)	3.465 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	TIN LEAD
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	14 mm

UPD4481321GF-A75Y Preview

DATA SHEET

MOS INTEGRATED CIRCUIT

PD4481161, 4481181, 4481321, 4481361

8M-BIT ZEROSB

SRAM

FLOW THROUGH OPERATION

Description

The

PD4481161 is a 524,288-word by 16-bit, the

PD4481181 is a 524,288-word by 18-bit, the

PD4481321 is a

262,144-word by 32-bit and the

PD4481361 is a 262,144-word by 36-bit ZEROSB static RAM fabricated with

advanced CMOS technology using full CMOS six-transistor memory cell.

The

PD4481161,

PD4481181,

PD4481321 and

PD4481361 are optimized to eliminate dead cycles for read to

write, or write to read transitions. These ZEROSB static RAMs integrate unique synchronous peripheral circuitry, 2-bit

burst counter and output buffer as well as SRAM core. All input registers are controlled by a positive edge of the

single clock input (CLK).

The

PD4481161,

PD4481181,

PD4481321 and

PD4481361 are suitable for applications which require

synchronous operation, high speed, low voltage, high density and wide bit configuration, such as buffer memory.

ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State

(“Sleep”). In the “Sleep” state, the SRAM internal state is preserved. When ZZ is set LOW again, the SRAM resumes

normal operation.

The

PD4481161,

PD4481181,

PD4481321 and

PD4481361 are packaged in 100-pin PLASTIC LQFP with a

1.4 mm package thickness for high density and low capacitive loading.

Features

•

Low voltage core supply : V

= 3.3 ± 0.165 V (-A65, -A75, -A85, -A65Y, -A75Y, -A85Y)

= 2.5 ± 0.125 V (-C75, -C85, -C75Y, -C85Y)

•

Synchronous operation

•

Operating temperature : T

= 0 to 70

°C

(-A65, -A75, -A85, -C75, -C85)

−40

+85 °C

(-A65Y, -A75Y, -A85Y, -C75Y, -C85Y)

•

100 percent bus utilization

•

Internally self-timed write control

•

Burst read / write : Interleaved burst and linear burst sequence

•

Fully registered inputs and outputs for flow through operation

•

All registers triggered off positive clock edge

•

3.3V or 2.5V LVTTL Compatible : All inputs and outputs

•

Fast clock access time : 6.5 ns (133 MHz), 7.5 ns (117 MHz), 8.5 ns (100 MHz)

•

Asynchronous output enable : /G

•

Burst sequence selectable : MODE

•

Sleep mode : ZZ (ZZ = Open or Low : Normal operation)

•

Separate byte write enable : /BW1 to /BW4 (

PD4481321 and

PD4481361)

/BW1 and /BW2 (

PD4481161 and

PD4481181)

•

Three chip enables for easy depth expansion

•

Common I/O using three state outputs

The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

Not all products and/or types are available in every country. Please check with an NEC Electronics

sales representative for availability and additional information.

Document No. M15561EJ3V0DS00 (3rd edition)

Date Published December 2002 NS CP(K)

Printed in Japan

The mark

shows major revised points.

2001

PD4481161, 4481181, 4481321, 4481361

Ordering Information

Part number

Access

Time

Clock

Frequency

MHz

133

117

100

133

117

100

133

117

100

133

117

100

117

100

117

100

117

100

117

100

2.5 ± 0.125

2.5 V LVTTL

3.3 V LVTTL

Note

3.3 V or 2.5 V LVTTL

3.3 V LVTTL

Note

3.3 V or 2.5 V LVTTL

3.3 V LVTTL

Note

3.3 V or 2.5 V LVTTL

Core Supply

Voltage

3.3 ± 0.165

3.3 V LVTTL

Note

3.3 V or 2.5 V LVTTL

I/O Interface

Operating

Temperature

°C

0 to 70

100-pin PLASTIC

LQFP (14 x 20)

Package

(1/2)

PD4481161GF-A65

PD4481161GF-A75

PD4481161GF-A85

PD4481181GF-A65

PD4481181GF-A75

PD4481181GF-A85

PD4481321GF-A65

PD4481321GF-A75

PD4481321GF-A85

PD4481361GF-A65

PD4481361GF-A75

PD4481361GF-A85

PD4481161GF-C75

PD4481161GF-C85

PD4481181GF-C75

PD4481181GF-C85

PD4481321GF-C75

PD4481321GF-C85

PD4481361GF-C75

PD4481361GF-C85

6.5

7.5

8.5

6.5

7.5

8.5

6.5

7.5

8.5

6.5

7.5

8.5

7.5

8.5

7.5

8.5

7.5

8.5

7.5

8.5

Note

Although 2.5V LVTTL interface can also be used, a performance becomes equivalent to -A75 (117 MHz).

Data Sheet M15561EJ3V0DS

PD4481161, 4481181, 4481321, 4481361

(2/2)

Part number

Access

Time

Clock

Frequency

MHz

133

117

100

133

117

100

133

117

100

133

117

100

117

100

117

100

117

100

117

100

2.5 ± 0.125

2.5 V LVTTL

3.3 V LVTTL

Note

3.3 V or 2.5 V LVTTL

3.3 V LVTTL

Note

3.3 V or 2.5 V LVTTL

3.3 V LVTTL

Note

3.3 V or 2.5 V LVTTL

Core Supply

Voltage

3.3 ± 0.165

3.3 V LVTTL

Note

3.3 V or 2.5 V LVTTL

I/O Interface

Operating

Temperature

°C

−40

+85

100-pin PLASTIC

LQFP (14 x 20)

Package

PD4481161GF-A65Y

PD4481161GF-A75Y

PD4481161GF-A85Y

PD4481181GF-A65Y

PD4481181GF-A75Y

PD4481181GF-A85Y

PD4481321GF-A65Y

PD4481321GF-A75Y

PD4481321GF-A85Y

PD4481361GF-A65Y

PD4481361GF-A75Y

PD4481361GF-A85Y

PD4481161GF-C75Y

PD4481161GF-C85Y

PD4481181GF-C75Y

PD4481181GF-C85Y

PD4481321GF-C75Y

PD4481321GF-C85Y

PD4481361GF-C75Y

PD4481361GF-C85Y

6.5

7.5

8.5

6.5

7.5

8.5

6.5

7.5

8.5

6.5

7.5

8.5

7.5

8.5

7.5

8.5

7.5

8.5

7.5

8.5

Note

Although 2.5V LVTTL interface can also be used, a performance becomes equivalent to -A75Y (117 MHz).

Data Sheet M15561EJ3V0DS

PD4481161, 4481181, 4481321, 4481361

Pin Configurations

/××× indicates active low signal.

100-pin PLASTIC LQFP (14

20)

[

PD4481161GF,

PD4481181GF]

Marking Side

/BW2

/BW1

/CKE

/CE2

ADV

CE2

CLK

/WE

A17

/CE

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

I/O9

I/O10

I/O11

I/O12

I/O13

I/O14

I/O15

I/O16

I/OP2, NC

A18

I/OP1, NC

I/O8

I/O7

I/O6

I/O5

I/O4

I/O3

I/O2

I/O1

MODE

A10

A11

A12

A13

A14

A15

Remark

Refer to

Package Drawing

for the 1-pin index mark.

Data Sheet M15561EJ3V0DS

A16

PD4481161, 4481181, 4481321, 4481361

Pin Identifications

[

PD4481161GF,

PD4481181GF]

Symbol

A0 to A18

Pin No.

37, 36, 35, 34, 33, 32, 100, 99, 82, 81,

44, 45, 46, 47, 48, 49, 50, 83, 80

I/O1 to I/O16

58, 59, 62, 63, 68, 69, 72, 73, 8, 9, 12, 13,

18, 19, 22, 23

I/OP1, NC

Note

I/OP2, NC

Note

ADV

/CE, CE2, /CE2

/WE

/BW1, /BW2

CLK

/CKE

MODE

98, 97, 92

93, 94

Synchronous Data In,

Synchronous / Asynchronous Data Out

Synchronous Data In (Parity),

Synchronous / Asynchronous Data Out (Parity)

Synchronous Address Load / Advance Input

Synchronous Chip Enable Input

Synchronous Write Enable Input

Synchronous Byte Write Enable Input

Asynchronous Output Enable Input

Clock Input

Synchronous Clock Enable Input

Asynchronous Burst Sequence Select Input

Have to tied to V

or V

during normal operation

15, 16, 41, 65, 91

14, 17, 40, 66, 67, 90

4, 11, 20, 27, 54, 61, 70, 77

5, 10, 21, 26, 55, 60, 71, 76

1, 2, 3, 6, 7, 25, 28, 29, 30, 38, 39, 42, 43,

51, 52, 53, 56, 57, 75, 78, 79, 84, 95, 96

Asynchronous Power Down State Input

Power Supply

Ground

Output Buffer Power Supply

Output Buffer Ground

No Connection

Description

Synchronous Address Input

Note

NC (No Connection) is used in the

PD4481161GF.

I/OP1 and I/OP2 are used in the

PD4481181GF.

Data Sheet M15561EJ3V0DS

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