U630H04
HardStore
512 x 8 nvSRAM
Features
F
Packages:
Description
F
High-performance CMOS nonvo-
latile static RAM 512 x 8 bits
F
25 ns Access Time
F
12 ns Output Enable Access Time
F
Unlimited Read and Write to
SRAM
F
Hardware STORE Initiation
(STORE Cycle Time < 10 ms)
F
Automatic STORE Timing
F
10 STORE cycles to EEPROM
F
10 years data retention in
EEPROM
F
Automatic RECALL on Power Up
F
Hardware RECALL Initiation
(RECALL Cycle Time < 20
µs)
F
Unlimited RECALL cycles from
EEPROM
F
Single 5 V
±
10 % Operation
F
Operating temperature ranges:
5
PDIP28 (600 mil)
SOP24 (300 mil)
F
F
0 to 70
°C
-40 to 85
°C
CECC 90000 Quality Standard
ESD characterization according
MIL STD 883C M3015.7-HBM
The U630H04 has two separate
modes of operation: SRAM mode
and nonvolatile mode, determined
by the state of the NE pin.
In SRAM mode, the memory ope-
rates as an ordinary static RAM. In
nonvolatile operation, data is trans-
ferred in parallel from SRAM to
EEPROM or from EEPROM to
SRAM. In this mode SRAM
functions are disabled.
The U630H04 is a fast static RAM
(25 ns), with a nonvolatile electri-
cally erasable PROM (EEPROM)
element incorporated in each static
memory cell. The SRAM can be
read and written an unlimited num-
ber of times, while independent
nonvolatile
data
resides
in
EEPROM.
Data transfers from the SRAM to
the EEPROM (the STORE opera-
tion), or from the EEPROM to the
SRAM (the RECALL operation) are
initiated through the state of the NE
pin.
The U630H04 combines the high
performance and ease of use of a
fast SRAM with nonvolatile data
integrity.
Once a STORE cycle is initiated,
further input or output are disabled
until the cycle is completed.
Internally, RECALL is a two step
procedure. First, the SRAM data is
cleared and second, the nonvola-
tile information is transferred into
the SRAM cells.
The RECALL operation in no way
alters the data in the EEPROM
cells. The nonvolatile data can be
recalled an unlimited number of
times.
Pin Configuration
Pin Description
NE
n.c.
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
PDIP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
W
n.c.
A8
n.c.
n.c.
G
n.c.
E
DQ7
DQ6
DQ5
DQ4
DQ3
NE
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VCC
n.c.
A7
W
G
A8
E
DQ7
DQ6
DQ5
DQ4
DQ3
Signal Name
A0 - A8
DQ0 - DQ7
E
G
W
NE
VCC
VSS
n.c.
Signal Description
Address Inputs
Data In/Out
Chip Enable
Output Enable
Write Enable
Nonvolatile Enable
Power Supply Voltage
Ground
not connected
SOP
Top View
Top View
August 07, 1998
27
U630H04
Block Diagram
EEPROM Array
16 x (32 x 8)
STORE
Row Decoder
A5
A6
A7
A8
SRAM
Array
16 Rows x
(32 x 8) Columns
RECALL
V
CC
V
SS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
Input Buffers
Column I/O
Column Decoder
Store/
Recall
Control
V
CC
A0 A1 A2 A3 A4
G
NE
E
W
Truth Table for SRAM Operations
Operating Mode
Standby/not selected
Internal Read
Read
Write
*
H or L
Characteristics
All voltages are referenced to V
SS
= 0 V (ground).
All characteristics are valid in the power supply voltage range and in the operating temperature range specified.
Dynamic measurements are based on a rise and fall time of
≤
5 ns, measured between 10 % and 90 % of V
I
, as well as
input levels of V
IL
= 0 V and V
IH
= 3 V. The timing reference level of all input and output signals is 1.5 V,
with the exception of the t
dis
-times and t
en
-times, in which cases transition is measured ± 200 mV from steady-state voltage.
E
H
L
L
L
NE
*
H
H
H
W
*
H
H
L
G
*
H
L
*
DQ0 - DQ7
High-Z
High-Z
Data Outputs Low-Z
Data Inputs High-Z
Absolute Maximum Ratings
a
Power Supply Voltage
Input Voltage
Output Voltage
Power Dissipation
Operating Temperature
Storage Temperature
C-Type
K-Type
Symbol
V
CC
V
I
V
O
P
D
T
a
T
stg
Min.
-0.5
-0.3
-0.3
Max.
7
V
CC
+0.5
V
CC
+0.5
1
Unit
V
V
V
W
°C
°C
°C
0
-40
-65
70
85
150
a: Stresses greater than those listed under „Absolute Maximum Ratings“ may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at condition above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
28
August 07, 1998
U630H04
Recommended
Operating Conditions
Power Supply Voltage
Input Low Voltage
Input High Voltage
Symbol
V
CC
V
IL
V
IH
-2 V at Pulse Width
10 ns permitted
Conditions
Min.
4.5
-0.3
2.2
Max.
5.5
0.8
V
CC
+0.3
Unit
V
V
V
C-Type
DC Characteristics
Operating Supply Current
b
Symbol
I
CC1
V
CC
V
IL
V
IH
t
c
V
CC
E
W
V
IL
V
IH
V
CC
E
t
c
Average Supply Current
at t
CR
= 200 ns
b
(Cycling CMOS Input Levels)
Standby Supply Current
d
(Stable CMOS Input Levels)
I
CC3
V
CC
W
V
IL
V
IH
V
CC
E
V
IL
V
IH
Conditions
Min.
= 5.5 V
= 0.8 V
= 2.2 V
= 25 ns
= 5.5 V
≥
V
CC
-0.2 V
≥
V
CC
-0.2 V
≤
0.2 V
≥
V
CC
-0.2 V
= 5.5 V
≥
V
IH
= 25 ns
= 5.5 V
≥
V
CC
-0.2 V
≤
0.2 V
≥
V
CC
-0.2 V
= 5.5 V
≥
V
CC
-0.2 V
≤
0.2 V
≥
V
CC
-0.2 V
15
Max.
90
K-Type
Unit
Min.
Max.
95
mA
Average Supply Current during
STORE
c
I
CC2
6
7
mA
Standby Supply Current
d
(Cycling TTL Input Levels)
I
CC(SB)1
30
34
mA
15
mA
I
CC(SB)
1
1
mA
b: I
CC1
and I
CC3
are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
The current I
CC1
is measured for WRITE/READ - ratio of 1/2.
c: I
CC2
is the average current required for the duration of the STORE cycle (STORE Cycle Time).
d: Bringing E
≥
V
IH
will not produce standby current levels until any nonvolatile cycle in progress has timed out. See MODE SELECTION
table. The current I
CC(SB)1
is measured for WRITE/READ - ratio of 1/2.
August 07, 1998
29
U630H04
C-Type
DC Characteristics
Symbol
V
CC
I
OH
I
OL
V
CC
V
OH
V
OL
V
CC
High
Low
Output Leakage Current
High at Three-State- Output
Low at Three-State- Output
I
OHZ
I
OLZ
I
IH
I
IL
V
IH
V
IL
V
CC
V
OH
V
OL
Conditions
Min.
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Input Leakage Current
V
OH
V
OL
I
OH
I
OL
= 4.5 V
=-4 mA
= 8 mA
= 4.5 V
= 2.4 V
= 0.4 V
= 5.5 V
= 5.5 V
= 0V
= 5.5 V
= 5.5 V
= 0V
1
-1
-1
1
µA
µA
1
-1
-1
1
µA
µA
2.4
0.4
-4
8
8
Max.
Min.
2.4
0.4
-4
Max.
V
V
mA
mA
K-Type
Unit
SRAM MEMORY OPERATIONS
Symbol
Min.
Alt.
t
AVAV
t
AVQV
t
ELQV
t
GLQV
t
EHQZ
t
GHQZ
t
ELQX
t
GLQX
t
AXQX
t
ELICCH
t
EHICCL
IEC
t
cR
t
a(A)
t
a(E)
t
a(G)
t
dis(E)
t
dis(G)
t
en(E)
t
en(G)
t
v(A)
t
PU
t
PD
5
0
3
0
25
25
25
25
12
13
13
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Max.
Unit
Switching Characteristics
No.
Read Cycle
1
2
3
4
5
6
7
8
9
Read Cycle Time
f
Address Access Time to Data Valid
g
Chip Enable Access Time to Data Valid
Output Enable Access Time to Data Valid
E HIGH to Output in High-Z
h
G HIGH to Output in High-Z
h
E LOW to Output in Low-Z
G LOW to Output in Low-Z
Output Hold Time after Addr. Change
g
10 Chip Enable to Power Active
e
11 Chip Disable to Power Standby
d, e
e:
f:
g:
h:
Parameter guaranteed but not tested.
Device is continuously selected with E and G both LOW.
Address valid prior to or coincident with E transition LOW.
Measured ± 200 mV from steady state output voltage.
30
August 07, 1998
U630H04
Read Cycle 1: Ai-controlled (during Read cycle: E = G = V
IL
, W = NE = V
IH
)
f
1
t
cR
Ai
Address Valid
2
t
a(A
)
DQi
Output
Previos
Data Valid
9
t
v(A)
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
Output Data
Valid
Read Cycle 2: G-, E-controlled (during Read cycle: W = NE = V
IH
)
g
1
t
cR
Ai
2
t
a(A)
Address Valid
3
t
a(E)
4
t
a(G)
E
7
t
en(E)
5
t
dis(E)
6
t
dis(G)
11
t
PD
G
DQi
Output
ACTIVE
High Impedance
10
t
PU
8
t
en(G)
AAAAAAAAAAA
Output Data
AAAAAAAAAAA
AAAAAAAAAAA
Valid
AAAAAAAAAAA
I
CC
STANDBY
No. Switching Characteristics
Write Cycle
12 Write Cycle Time
13 Write Pulse Width
14 Write Pulse Width Setup Time
15 Address Setup Time
16 Address Valid to End of Write
17 Chip Enable Setup Time
18 Chip Enable to End of Write
19 Data Setup Time to End of Write
20 Data Hold Time after End of Write
21 Address Hold after End of Write
22 W LOW to Output in High-Z
h, i
23 W HIGH to Output in Low-Z
Symbol
Min.
Alt. #1
t
AVAV
t
WLWH
t
WLEH
t
AVWL
t
AVWH
t
ELWH
t
ELEH
t
DVWH
t
WHDX
t
WHAX
t
WLQZ
t
WHQX
t
DVEH
t
EHDX
t
EHAX
t
AVEL
t
AVEH
Alt. #2
t
AVAV
IEC
t
cW
t
w(W)
Max.
Unit
25
20
20
0
20
20
20
12
0
0
10
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
su(W)
t
su(A-WH)
t
su(A-WH)
t
su(E)
t
w(E)
t
su(D)
t
h(D)
t
h(A)
t
dis(W)
t
en(W)
August 07, 1998
31
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