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Datasheet> All Categories > storage> storage> U62H824PC35
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U62H824PC35

Description
Standard SRAM, 8KX24, 35ns, CMOS, PQCC52, PLASTIC, LCC-52
Categorystorage    storage   
File Size169KB，11 Pages
ManufacturerAlliance Memory
Download Datasheet Parametric View All

U62H824PC35 Overview

Standard SRAM, 8KX24, 35ns, CMOS, PQCC52, PLASTIC, LCC-52

U62H824PC35 Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerAlliance Memory
Parts packaging codeLCC
package instructionQCCJ,
Contacts52
Reach Compliance Codecompliant
ECCN codeEAR99
Maximum access time35 ns
JESD-30 codeS-PQCC-J52
length19.1262 mm
memory density196608 bit
Memory IC TypeSTANDARD SRAM
memory width24
Number of functions1
Number of terminals52
word count8192 words
character code8000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize8KX24
Package body materialPLASTIC/EPOXY
encapsulated codeQCCJ
Package shapeSQUARE
Package formCHIP CARRIER
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)240
Certification statusNot Qualified
Maximum seat height5.1 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationQUAD
Maximum time at peak reflow temperature30
width19.1262 mm

U62H824PC35 Preview

U62H824
Fast 8K x 24 SRAM
Features
!
196 608 bit static CMOS RAM
!
35 ns Access Time
!
Fully static Read and Write
!
!
!
!
!
!
!
!
Description
The U62H824 is a static RAM
manufactured using a CMOS pro-
cess technology. The device inte-
grates an 8K x 24 SRAM core with
multiple chip enable inputs, output
enable, and an externally control-
led single address pin multiplexer.
These functions allow for direct
connection
to
the
Motorola
DSP56k Digital Signal Processor
Family and provide a very efficient
means for implementation of a
reduced parts count system requi-
ring no additional interface logic.
The avialability of multiple chip
enable (E1 and E2) and output
enable (G) inputs provides for
greater system flexibility when mul-
tiple devices are used. With either
chip enable unasserted, the device
will enter standby mode, useful in
low-power applications. A single
on-chip multiplexer selects A12 or
X/Y as the highest order address
input depending upon the state of
the V/S control input. This feature
allows one physical static RAM
component to efficiently store pro-
gram and vector or scalar ope-
rands
by
dynamically
re-
partitioning the RAM array.
Typical applications will logically
map vector operands into upper
memory with scalar operands
being stored in lower memory.
An application example is at the
end of this document for additional
information.
Multiple power and ground pins
have been utilized to minimize
effectes induced by output noice.
!
!
!
!
operations
Equal address and chip
enable access times
Single bit on-chip address
multiplexer
Active high and active low
chip enable inputs
Output enable controlled three-
state outputs
TTL/CMOS-compatible
Low power standby mode
Power supply voltage 5 V
Operating temperature range
0 to 70
°C
-40 to 85
°C
-40 to 125 °C
QS 9000 Quality Standard
ESD protection > 2000 V
(MIL STD 883C M3015.7)
Latch-up immunity > 100 mA
Package: PLCC52
Pin Configuration
Pin Description
VCC
A10
A11
A12
X/Y
V/S
NC
A0
A1
A2
A3
A4
7
DQ0
DQ1
DQ2
VSS
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
VSS
DQ9
DQ10
8
9
10
11
12
13
14
15
16
17
18
19
20
6
5
4
3
2
1 52 51 50 49 48 47
46
45
44
43
42
41
40
39
38
37
36
35
DQ23
DQ22
DQ21
VSS
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
VSS
DQ14
DQ13
A5
Signal Name
A0 - A11
A12, X/Y
V/S
DQ0 - DQ23
E1, E2
G
W
VCC
VSS
NC
Signal Description
Address Inputs
Multiplexed Address
Address Multiplexer Control
Data Input / Output
Chip Enable
Output Enable
Write Enable
Power Supply Voltage
Ground
Not Connected
21 22 23 24 25 26 27 28 29 30 31 32 33
VCC
VSS
W
NC
G
A9
A8
A7
A6
E1
E2
DQ12
DQ11
34
For proper operation of the device, all V
SS
pins must be connected to ground.
November 26, 2002
1
U62H824
Block Diagram
A0
Memory Cell
Row
A5
A10
A11
Decoder
Array
256 Rows x
768 Columns
V
CC
V
SS
DQ0
DQ23
E1
E2
W
G
Input Data
Control
Column I/O
Column Decoder
&
&
X/Y
A12
V/S
A12i
1
0 Q
2 to 1 MUX
&
A6
A9
(LSB)
(MSB)
Truth Table
Supply
Current
I
CC(SB)
I
CC(SB)
I
CC(OP)
I
CC(OP)
I
CC(OP)
I
CC(OP)
I
CC(OP)
I/O
Status
High - Z
High - Z
High - Z
Data Out
Data Out
Data In
Data In
Mode
Not Selected
Not Selected
Output Disable
Read Using X/Y
Read Using A12
Write Using X/Y
Write Using A12
* H or L
E1
H
*
L
L
L
L
L
E2
*
L
H
H
H
H
H
G
*
*
H
L
L
*
*
W
*
*
H
H
H
L
L
V/S
*
*
*
H
L
H
L
2
November 26, 2002
U62H824
Characteristics
All voltages are referenced to V
SS
= 0 V (ground).
All characteristics are valid in the power supply voltage range and in the operating temperature range specified.
Dynamic measurements are based on a rise and fall time of
≤
5 ns, measured between 10 % and 90 % of V
I
, as well as
input levels of V
IL
= 0 V and V
IH
= 3 V. The timing reference level of all input and output signals is 1.5 V,
with the exception of the t
dis
-times and t
en
-times, in which cases transition is measured
±
200 mV from steady-state voltage.
Absolute Maximum Ratings
a
Power Supply Voltage
Input Voltage
Output Voltage
Power Dissipation
Operating Temperature
C-Type
K-Type
A-Type
Symbol
V
CC
V
I
V
O
P
D
T
a
Min.
-0.5
-0.5
-0.5
-
0
-40
-40
-65
Max.
7
V
CC
+ 0.5
b
V
CC
+ 0.5
b
1.75
70
85
125
150
20
Unit
V
V
V
W
°C
°C
°C
°C
mA
Storage Temperature
Output Short-Circuit Current
at V
CC
= 5 V and V
O
= 0 V
c
a
T
stg
|I
OS
|
b
c
Stresses greater than those listed under „Absolute Maximum Ratings“ may cause permanent damage to the device. This is a stress rating
only, and functional operation of the device at condition above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability
Maximum voltage is 7 V
Not more than 1 output should be shorted at the same time. Duration of the short circuit should not exceed 30 s.
Recommended
Operating Conditions
Power Supply Voltage
Input Low Voltage
d
Input High Voltage
d
Symbol
V
CC
V
IL
V
IH
Conditions
Min.
4.5
-0.3
2.2
Max.
5.5
0.8
V
CC
+ 0.3
Unit
V
V
V
-2 V at Pulse Width 10 ns
November 26, 2002
3
U62H824
Electrical Characteristics
Supply Current - Operating Mode
Symbol
I
CC(OP)
Conditions
V
CC
V
E1
V
E2
V
G
other inputs
I
out
t
cW
C/K-Type
A-Type
V
CC
V
E1
V
E2
all inputs
C-Type
K-Type
A-Type
Supply Current - Standby Mode
(TTL level)
I
CC(SB)1
V
CC
V
E1
V
E2
all inputs
V
CC
I
OH
I
OL
V
CC
V
IH
V
IL
V
CC
V
OH
V
OL
V
CC
V
OH
V
OL
V
G
=
=
=
=
5.5 V
2.2 V
0.8 V
V
IH
or V
IL
2.4
0.4
2
-2
-4
8
2
-2
=
=
=
=
=
=
=
5.5 V
0.8 V
2.2 V
2.2 V
V
IL
or V
IH
0 mA
35 ns
170
180
= 5.5 V
= V
CC
- 0.2 V
= 0.2 V
≥
V
CC
- 0.2 V
or
≤
0.2 V
6
8
10
15
mA
mA
mA
mA
mA
mA
Min.
Max.
Unit
Supply Current - Standby Mode
(CMOS level)
I
CC(SB)
Output High Voltage
Output Low Voltage
Input High Leakage Current
Input Low Leakage Current
Output High Current
Output Low Current
Output Leakage Current
High at Three-State Outputs
Low at Three-State Outputs
V
OH
V
OL
I
IH
I
IL
I
OH
I
OL
I
OHZ
I
OLZ
= 4.5 V
= -4.0 mA
= 8.0 mA
= 5.5 V
= 5.5 V
= 0 V
= 4.5 V
= 2.4 V
= 0.4 V
= 5.5 V
= 5.5 V
= 0 V
= V
IH
V
V
µA
µA
mA
mA
µA
µA
4
November 26, 2002
U62H824
Switching Characteristics
Read Cycle
Read Cycle Time
Address Access Time to Data Valid
MUX Control to Data Valid
Chip Enable Access Time to Data Valid
G LOW to Data Valid
Output Hold Time from Address Change
Output Hold Time from MUX Control Change
E1 LOW or E2 HIGH to Output in Low-Z
G LOW to Output in Low-Z
E1 HIGH or E2 LOW to Output in High-Z
G HIGH to Output in High-Z
t
LZCE
t
LZOE
t
HZCE
t
HZOE
Symbol
Alt.
t
WC
t
WP
t
WP
t
AS
IEC
t
cW
t
w(W)
t
su(W)
t
su(A)
t
su(VS)
t
AW
t
su(A-WH)
t
su(VS-WH)
t
su(A-E)
t
su(VS-E)
t
CW
t
CW
t
DS
t
DH
t
AH
t
su(E)
t
w(E)
t
su(D)
t
h(D)
t
h(A)
t
h(VS)
t
LZWE
t
HZWE
5
t
en(W)
t
dis(W)
Min.
35
20
20
0
0
30
30
30
30
20
20
15
0
0
0
5
15
t
ACE
t
OE
t
OH
Symbol
Alt.
t
RC
t
AA
IEC
t
cR
t
a(A)
t
a(VS)
t
a(E)
t
a(G)
t
v(A)
t
v(VS)
t
en(E)
t
en(G)
t
dis(E)
t
dis(G)
35
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
5
0
0
15
15
Min.
35
35
35
35
15
ns
ns
ns
ns
ns
ns
ns
ns
35
Max.
Unit
ns
ns
Switching Characteristics
Write Cycle
Write Cycle Time
Write Pulse Width
Write Pulse Width Setup Time
Address Setup Time
MUX Control Setup Time
Address Valid to End of Write
MUX Control Valid to End of Write
Adress Valid to End of Write
MUX Control Valid to End of Write
Chip Enable Setup Time
Pulse Width Chip Enable
Data Setup Time
Data Hold Time
Address Hold from End of Write
MUX Control from End of Write
W HIGH to Output in Low-Z
W LOW to Output in High-Z
November 26, 2002
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