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SN54CBT16209, SN74CBT16209
18-BIT BUS-EXCHANGE SWITCHES
SCDS006G – NOVEMBER 1992 – REVISED JUNE 1996
D
D
D
5-Ω Switch Connection Between Two Ports
TTL-Compatible Input and Output Levels
Package Options Include Plastic Thin
Shrink Small-Outline (DGG), 300-mil Shrink
Small-Outline (DL), and 380-mil Fine-Pitch
Ceramic Flat (WD) Packages
SN54CBT16209 . . . WD PACKAGE
SN74CBT16209 . . . DGG OR DL PACKAGE
(TOP VIEW)
description
The ’CBT16209 provide 18 bits of high-speed
TTL-compatible bus switching or exchanging.
The low on-state resistance of the switch allows
connections to be made with minimal propagation
delay.
The devices operate as an 18-bit bus switch or a
9-bit bus exchanger, which provides data
exchanging between the four signal ports via the
data-select (S0 – S2) terminals.
The SN54CBT16209 is characterized for
operation from – 55°C to 125°C. The
SN74CBT16209 is characterized for operation
from – 40°C to 85°C.
FUNCTION TABLE
S2
L
L
L
L
H
H
H
H
S1
L
L
H
H
L
L
H
H
S0
L
H
L
H
L
H
L
H
A1
Z
B1
B2
Z
Z
Z
B1
B2
A2
Z
Z
Z
B1
B2
Z
B2
B1
FUNCTION
Disconnect
A1 to B1
A1 to B2
A2 to B1
A2 to B2
Disconnect
A1 to B1, A2 to B2
A1 to B2, A2 to B1
S0
1A1
1A2
GND
2A1
2A2
V
CC
3A1
3A2
GND
4A1
4A2
5A1
5A2
GND
6A1
6A2
7A1
7A2
GND
8A1
8A2
9A1
9A2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
S1
S2
1B1
1B2
2B1
2B2
GND
3B1
3B2
GND
4B1
4B2
5B1
5B2
GND
6B1
6B2
7B1
7B2
GND
8B1
8B2
9B1
9B2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
©
1996, Texas Instruments Incorporated
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•
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1
SN54CBT16209, SN74CBT16209
18-BIT BUS-EXCHANGE SWITCHES
SCDS006G – NOVEMBER 1992 – REVISED JUNE 1996
logic diagram
1A1
2
One of Nine Channels
46
1B1
1A2
3
45
1B2
Flow Control
S0
S1
S2
1
48
47
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
Input voltage range, V
I
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, I
IK
(V
I
< 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 50 mA
Maximum power dissipation at T
A
= 55°C (in still air) (see Note 2): DGG package . . . . . . . . . . . . . . . 0.85 W
DL package . . . . . . . . . . . . . . . . . . . 1.2 W
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
For more information, refer to the
Package Thermal Considerations
application note in the
ABT Advanced BiCMOS Technology Data
Book.
recommended operating conditions
SN54CBT16209 SN74CBT16209
MIN
VCC
VIH
VIL
TA
Supply voltage
High-level input voltage
Low-level input voltage
Operating free-air temperature
– 55
4
2
0.8
125
– 40
MAX
5.5
MIN
4
2
0.8
85
MAX
5.5
UNIT
V
V
V
°C
2
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SN54CBT16209, SN74CBT16209
18-BIT BUS-EXCHANGE SWITCHES
SCDS006G – NOVEMBER 1992 – REVISED JUNE 1996
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
II
ICC
∆I
CC‡
Ci
Cio(OFF)
ron§
VCC = 4.5 V,
VCC = 0,
VCC = 5.5 V,
VCC = 5.5 V,
Control pins
Control pins
VCC = 5.5 V,
VI = 3 V or 0
VO = 3 V or 0,
VCC = 4.5 V
TEST CONDITIONS
II = – 18 mA
VI = 5.5 V
VI = 5.5 V or GND
IO = 0,
One input at 3.4 V,
S0, S1, or S2 = VCC
VI = 0,
VI = 0,
VI = 2.4 V,
II = 64 mA
II = 30 mA
II = 15 mA
VI = VCC or GND
Other inputs at VCC or GND
4
7.5
4
4
6
8
8
15
Ω
MIN
TYP†
MAX
–1.2
10
±1
3
2.5
UNIT
V
µA
µA
mA
pF
pF
† All typical values are at VCC = 5 V, TA = 25°C.
‡ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
§ Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by
the lower of the voltages of the two (A or B) terminals.
switching characteristics over recommended operating free-air temperature range, C
L
= 50 pF
(unless otherwise noted) (see Figure 1)
SN54CBT16209
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 5 V
±
0.5 V
MIN
tpd¶
tpd
ten
A or B
S
S
B or A
A or B
MAX
0.8
2
1.7
13.1
15.3
14
16
2.6
2.7
VCC = 4 V
MIN
MAX
SN74CBT16209
VCC = 5 V
±
0.5 V
MIN
MAX
0.25
10.2
10.6
VCC = 4 V
MIN
MAX
0.25
11.3
11.5
ns
ns
UNIT
tdis
S
A or B
1
13.2
14.5
1.2
11.3
12.1
ns
¶ This parameter is warranted but not production tested. The propagation delay is based on the RC time constant of the typical on-state resistance
of the switch and a load capacitance of 50 pF, when driven by an ideal voltage source (zero output impedance).
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3
SN54CBT16209, SN74CBT16209
18-BIT BUS-EXCHANGE SWITCHES
SCDS006G – NOVEMBER 1992 – REVISED JUNE 1996
PARAMETER MEASUREMENT INFORMATION
7V
From Output
Under Test
CL = 50 pF
(see Note A)
500
Ω
S1
Open
GND
500
Ω
Output
Control
(low-level
enabling)
tPZL
3V
1.5 V
1.5 V
0V
tPLZ
3.5 V
1.5 V
tPHZ
VOH
1.5 V
VOH – 0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOL + 0.3 V
VOL
TEST
tpd
tPLZ/tPZL
tPHZ/tPZH
S1
Open
7V
Open
LOAD CIRCUIT
3V
Input
tPLH
1.5 V
1.5 V
0V
tPHL
VOH
Output
1.5 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
1.5 V
VOL
Output
Waveform 1
S1 at 7 V
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
tPZH
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50
Ω,
tr 2.5 ns, tf 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
v
v
v
Figure 1. Load Circuit and Voltage Waveforms
4
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