KM68FV1000, KM68FS1000, KM68FR1000 Family
Document Title
128K x8 bit Super Low Power and Low Voltage Full CMOS Static RAM
CMOS SRAM
Revision History
Revision No. History
0.0
0.1
Initial draft
Revise
- Erase 100ns from KM68FS1000 Family
- Add 150ns for KM68FS1000 Family
- Add 32-sTSOP1 new package
- Add high power version
I
SB1
=5.0µA(Max)
- Change V
DR
(Min) 1.0 to 1.5V
Finalize
- Concept change high power version to low low power version
I
SB1
=5.0µA(Max)
- Change super low power version with special handling
I
SB1
=1.0µA(Max)
- Icc & Icc1(Read) decrease 10 to 5mA
Revise
- Change datasheet format
- Remove reverse type package from product
- Remove reserved speed bin(100ns)
Revise
- Add CSP type packaged product.
- Improved I
CC2
Draft Date
March 15, 1996
July 7, 1996
Remark
Advance
Preliminary
1.0
December 1, 1996
Final
2.0
February 26, 1998
Final
3.0
July 29, 1998
Final
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserves the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
1
Revision 3.0
July 1998
KM68FV1000, KM68FS1000, KM68FR1000 Family
CMOS SRAM
128K x8 bit Super Low Power and Low Voltage Full CMOS Static RAM
FEATURES
•
Process Technology : Full CMOS
•
Organization : 128K x8 bit
•
Power Supply Voltage
KM68FV1000 Family : 3.0V ~ 3.6V
KM68FS1000 Family : 2.3V ~ 3.3V
KM68FR1000 Family : 1.8V ~ 2.7V
•
Low Data Retention Voltage : 1.5V(Min)
•
Three state output and TTL Compatible
•
Package Type : 32-SOP-525, 32-TSOP1-0820F,
32-TSOP1-0813.4F, 48-CSP
GENERAL DESCRIPTION
The KM68FV1000, KM68FS1000 and KM68FR1000 families
are fabricated by SAMSUNG′s advanced Full CMOS process
technology. The families support various operating temperature
range and have various package types for user flexibility of sys-
tem design. The families also support low data retention voltage
for battery back-up operation with low data retention current.
PRODUCT FAMILY
Power Dissipation
Product Family Operating Temperature Vcc Range
Speed(ns)
Standby
(I
SB1
, Max)
Operating
(I
CC2
, Max)
40mA
35mA
30mA
5µA
2)
15mA
40mA
35mA
30mA
15mA
32-SOP
32-TSOP1
Forward
32-sTSOP1
Forward
48-CSP
PKG Type
KM68FV1000
KM68FS1000
KM68FR1000
KM68FV1000I
KM68FS1000I
KM68FR1000I
Industrial(-40~85°C)
Commercial(0~70°C)
3.0~3.6V
2.3~3.3V
1.8~2.7V
3.0~3.6V
2.3~3.3V
1.8~2.7V
70
1)
/85@V
CC
=3.3±0.3V
70
1)
/85@V
CC
=3.0±0.3V
120
1)
/150@V
CC
=2.5±0.2V
300
1)
@V
CC
=2.0±0.2V
70
1)
/85@V
CC
=3.3±0.3V
70
1)
/85/100@V
CC
=3.0±0.3V
120
1)
/150@V
CC
=2.5±0.2V
300 @V
CC
=2.0±0.2V
1)
1. The parameter is measured with 30pF test load.
2. 1µA for super low power version with special handling.
PIN DESCRIPTION
N.C
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
A15
CS2
WE
A13
A8
A9
A11
OE
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
C
D
E
F
G
H
A
B
A11
A9
A8
A13
WE
CS2
A15
VCC
N.C
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
6
OE
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
A1
A2
A3
FUNCTIONAL BLOCK DIAGRAM
Clk gen.
Precharge circuit.
A8
A13
A15
A16
A7
A6
A5
A4
A14
A12
32-TSOP
32-sTSOP
Type1-Forward
32-SOP
Row
select
Memory array
1024 rows
128×8 columns
2
3
4
5
A
0
I/O
5
I/O
6
V
SS
V
CC
I/O
7
I/O
8
A
9
A
1
A
2
CS
2
WE
NC
A
3
A
4
A
5
A
6
A
7
A
8
I/O
1
I/O
1
I/O
2
V
CC
V
SS
I/O
8
Data
cont
Data
cont
A10
A0
I/O Circuit
Column select
NC
OE
A
10
CS
1
A
11
NC
A
16
A
12
A
15
A
13
I/O
3
I/O
4
A
14
CS1
CS2
WE
OE
A1
A2
A3 A9
A11
48-CSP - TOP VIEW
Control
logic
Name
Function
Name
OE
WE
Function
Output Enable Input
Write Enable Input
Name
Vcc
Vss
Function
Power
Ground
Name
Function
CS
1
,CS
2
Chip Select Input
N.C.
No Connection
I/O
1
~I/O
8
Data Inputs/Outputs
A
0
~A
16
Address Inputs
SAMSUNG ELECTRONICS CO., LTD.
reserves the right to change products and specifications without notice.
2
Revision 3.0
July 1998
KM68FV1000, KM68FS1000, KM68FR1000 Family
PRODUCT LIST
Commercial Temperature Products(0~70
°
C)
Part Name
KM68FV1000G-7
KM68FV1000G-8
KM68FV1000T-7
KM68FV1000T-8
KM68FS1000G-12
KM68FS1000G-15
KM68FS1000T-12
KM68FS1000T-15
KM68FS1000TG-12
KM68FS1000TG-15
Function
32-SOP, 70ns, 3.3V
32-SOP, 85ns, 3.3V
32-TSOP1 F, 70ns, 3.3V
32-TSOP1 F, 85ns, 3.3V
32-SOP, 120/70ns, 2.5/3.0V
32-SOP, 150/85ns, 2.5/3.0V
32-TSOP1 F, 120/70ns, 2.5/3.0V
32-TSOP1 F, 150/85ns, 2.5/3.0V
32-sTSOP1 F, 120/70ns, 2.5/3.0V
32-sTSOP1 F, 150/85ns, 2.5/3.0V
CMOS SRAM
Industrial Temperature Products(-40~85
°
C)
Part Name
KM68FV1000GI-7
KM68FV1000GI-8
KM68FV1000TI-7
KM68FV1000TI-8
KM68FS1000GI-12
KM68FS1000GI-15
KM68FS1000TI-12
KM68FS1000TI-15
KM68FS1000TGI-12
KM68FS1000TGI-15
KM68FS1000ZI-15
KM68FR1000GI-30
KM68FR1000TI-30
KM68FR1000TGI-30
KM68FR1000ZI-30
Function
32-SOP, 70ns, 3.3V
32-SOP, 85ns, 3.3V
32-TSOP1 F, 70ns, 3.3V
32-TSOP1 F, 85ns, 3.3V
32-SOP, 120/70ns, 2.5/3.0V
32-SOP, 150/85ns, 2.5/3.0V
32-TSOP1 F, 120/70ns, 2.5/3.0V
32-TSOP1 F, 150/85ns, 2.5/3.0V
32-sTSOP1 F, 120/70ns, 2.5/3.0V
32-sTSOP1 F, 150/85ns, 2.5/3.0V
48-CSP, 150/100ns, 2.5/3.0V
32-SOP, 300ns, 2.0/2.5V
32-TSOP1 F, 300ns, 2.0/2.5V
32-sTSOP1 F, 300ns, 2.0/2.5V
48-CSP, 300ns, 2.0/2.5V
KM68FR1000G-30
KM68FR1000T-30
KM68FR1000TG-30
32-SOP, 300ns, 2.0/2.5V
32-TSOP1 F, 300ns, 2.0/2.5V
32-sTSOP1 F, 300ns, 2.0/2.5V
FUNCTIONAL DESCRIPTION
CS
1
H
X
1)
L
L
L
CS
2
X
1)
L
H
H
H
OE
X
1)
X
1)
H
L
X
1)
WE
X
1)
X
1)
H
H
L
I/O
High-Z
High-Z
High-Z
Dout
Din
Mode
Deselected
Deselected
Output Disabled
Read
Write
Power
Standby
Standby
Active
Active
Active
1. X means don′t care. (Must be high or low states)
ABSOLUTE MAXIMUM RATINGS
1)
Item
Voltage on any pin relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
Storage temperature
Operating Temperature
Soldering temperature and time
Symbol
V
IN
,V
OUT
V
CC
P
D
T
STG
T
A
-40 to 85
T
SOLDER
260°C, 5sec (Lead Only)
Ratings
-0.2 to 3.6V
2)
-0.2 to 4.0V
3)
1.0
-55 to 150
0 to 70
Unit
V
V
W
°C
°C
°C
-
Remark
-
-
-
-
KM68FV1000, KM68FS1000, KM68FR1000
KM68FV1000I, KM68FS1000I, KM68FR1000I
-
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. V
IN
/V
OUT
=-0.2 to 3.9V for KM68FV1000 Family.
3. Maximum V
CC
=-0.2 to 4.6V for KM68FV1000 Family.
3
Revision 3.0
July 1998
KM68FV1000, KM68FS1000, KM68FR1000 Family
RECOMMENDED DC OPERATING CONDITIONS
1)
Item
Symbol
Product
KM68FV1000 Family
Supply voltage
Vcc
KM68FS1000 Family
KM68FR1000 Family
Ground
Vss
All Family
KM68FV1000 Family
KM68FS1000 Family
Vcc=3.3±0.3V
Vcc=3.0±0.3V
Vcc=2.5±0.2V
KM68FR1000 Family
Input low voltage
V
IL
All Family
Vcc=2.5±0.2V
Vcc=2.0±0.2V
Min
3.0
2.3
1.8
0
2.2
2.2
2.0
2.0
1.6
-0.2
3)
-
-
Typ
3.3
2.5/3.0
2.0/2.5
0
CMOS SRAM
Max
3.6
3.3
2.7
0
Unit
V
V
Input high voltage
V
IH
Vcc+0.2
2)
V
0.4
V
Note
1 Commercial Product : T
A
=0 to 70°C, unless otherwise specified
Industrial Product : T
A
=-40 to 85°C, unless otherwise specified
2. Overshoot : Vcc + 1.0V in case of pulse width
≤20ns
3. Undershoot : -1.0V in case of pulse width
≤20ns
4. Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE
1)
(f=1MHz, T
A
=25°C)
Item
Input capacitance
Input/Output capacitance
1. Capacitance is sampled, not 100% tested
Symbol
C
IN
C
IO
Test Condition
V
IN
=0V
V
IO
=0V
Min
-
-
Max
8
10
Unit
pF
pF
DC AND OPERATING CHARACTERISTICS
Item
Input leakage current
Output leakage current
Operating power supply current
Symbol
I
LI
I
LO
I
CC
I
CC1
Average operating current
I
CC2
Cycle time=Min, 100% duty, I
IO
=0mA,
CS
1
=V
IL
, CS
2
=V
IH,
V
IN
=V
IL
or V
IH
Test Conditions
V
IN
=Vss to Vcc
CS
1
=V
IH
or CS
2
=V
IL
or OE=V
IH
or WE=V
IL,
V
IO
=Vss to Vcc
I
IO
=0mA, CS
1
=V
IL
, CS
2
=V
IH
, V
IN
=V
IL
or V
IH
, Read
Cycle time=1
µs
, 100% duty, I
IO
=0mA, CS
1
≤0.2V,
CS
2
≥V
CC
-0.2V, V
IN
≤0.2V
or V
IN
≥V
CC
-0.2V
Min
-1
-1
-
Read
Write
-
-
-
-
-
Typ
-
-
-
-
10
-
-
-
Max
1
1
2
3
15
35
1)
30
15
Unit
µA
µA
mA
mA
Vcc=3.3V@70ns
Vcc=2.7V@120ns
Vcc=2.2V@300ns
2.1mA at Vcc=3.0/3.3V
mA
Output low voltage
V
OL
I
OL
0.5mA at Vcc=2.5V
0.33mA at Vcc=2.0V
-1.0mA at Vcc=3.0/3.3V
-
-
0.4
V
2.4
2.0
1.6
-
-
-
-
-
-
-
-
-
-
0.3
5
1)
mA
µA
V
Output high voltage
V
OH
I
OH
-0.5mA at Vcc=2.5V
-0.44mA at Vcc=2.0V
Standby Current(TTL)
Standby Current(CMOS)
I
SB
I
SB1
CS
1
=V
IH
or
CS
2
=V
IL,
Other inputs=V
IL
or V
IH
CS
1
≥Vcc-0.2V,
CS
2
≥Vcc-0.2V
or CS
2
≤0.2V,
Other inputs=0~Vcc
1. KM68FV1000 Family = 40mA
2. Super low power product = 1µA with special handling.
4
Revision 3.0
July 1998
KM68FV1000, KM68FS1000, KM68FR1000 Family
AC OPERATING CONDITIONS
TEST CONDITIONS
(Test Load and Test Input/Output Reference)
Input pulse level : 0.4 to 2.2V for Vcc=3.3V, 3.0V, 2.5V
0.4 to 1.8V for Vcc=2.0V
Input rising and falling time : 5ns
Input and output reference voltage : 1.5V for Vcc=3.3V, 3.0V
1.1V for Vcc=2.5V
0.9V for Vcc=2.0V
Output load (See right) :C
L
=100pF+1TTL
C
L
=30pF+1TTL
CMOS SRAM
V
TM
3)
R
1
2)
C
L
1)
R
2
2)
1. Including scope and jig capacitance
2. R
1
=3070Ω
,
R
2
=3150Ω
3. V
TM
=2.8V for V
CC
=3.0/3.3V
2.3V for V
CC
=2.5V
1.8V for V
CC
=2.0V
AC CHARACTERISTICS
(Commercial product :T
A
=0 to 70°C, Industrial product : T
A
=-40 to 85°C
KM68FV1000 Family : Vcc=3.0~3.6V, KM68FS1000 Family : Vcc=2.3~3.3V,
KM68FR1000 Family : Vcc=1.8~2.7V)
Speed Bins
Parameter List
Symbol
70ns
85ns
100ns
120ns
150ns
300ns
Units
Min Max Min Max Min Max Min Max Min Max Min Max
Read cycle time
Address access time
Chip select to output
Output enable to valid output
Read Chip select to low-Z output
Output enable to low-Z output
Chip disable to high-Z output
Output disable to high-Z output
Output hold from address change
Write cycle time
Chip select to end of write
Address set-up time
Address valid to end of write
Write
Write pulse width
Write recovery time
Write to output high-Z
Data to write time overlap
Data hold from write time
End write to output low-Z
t
RC
t
AA
t
CO1
, t
CO2
t
OE
t
LZ1
, t
LZ2
t
OLZ
t
HZ1
, t
HZ2
t
OHZ
t
OH
t
WC
t
CW
t
AS
t
AW
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
70
-
-
-
10
5
0
0
10
70
65
0
65
55
0
0
30
0
5
-
70
70
35
-
-
25
25
-
-
-
-
-
-
-
25
-
-
-
85
-
-
-
10
5
0
0
15
85
70
0
70
60
0
0
35
0
5
-
85
85
45
-
-
25
25
-
-
-
-
-
-
-
25
-
-
-
100
-
-
-
10
5
0
0
15
100
80
0
80
70
0
0
40
0
5
-
100
100
50
-
-
30
30
-
-
-
-
-
-
-
30
-
-
-
120
-
-
-
10
5
0
0
15
120
100
0
100
80
0
0
50
0
5
-
120
120
60
-
-
35
35
-
-
-
-
-
-
-
35
-
-
-
150
-
-
-
20
10
0
0
15
150
120
0
120
100
0
0
60
0
5
-
150
150
75
-
-
40
40
-
-
-
-
-
-
-
40
-
-
-
300
-
-
-
50
30
0
0
30
300
300
0
300
200
0
0
120
0
20
-
300
300
150
-
-
60
60
-
-
-
-
-
-
-
60
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DATA RETENTION CHARACTERISTICS
Item
Vcc for data retention
Data retention current
Data retention set-up time
Recovery time
Symbol
V
DR
I
DR
t
SDR
t
RDR
Test Condition
CS
1
≥Vcc-0.2V
1)
Vcc=3.0V, CS
1
≥Vcc-0.2V
1)
See data retention waveform
Min
1.5
-
0
t
RC
Typ
-
-
-
-
Max
3.6
5.0
2)
-
-
Unit
V
µA
ns
1. CS
1
≥Vcc-0.2V,
CS
2
≥Vcc-0.2V(CS
1
controlled) or CS
2
≤0.2V(CS
2
controlled)
2. Super low power product = 1µA with special handling.
5
Revision 3.0
July 1998
京公网安备 11010802033920号
EEWORLD
