2.5V ZERO DELAY CLOCK BUFFER, SPREAD SPECTRUM COMPATIBLE
COMMERCIAL TEMPERATURE RANGE
2.5V ZERO DELAY
CLOCK BUFFER, SPREAD
SPECTRUM COMPATIBLE
FEATURES:
DESCRIPTION:
IDT23S09T
ADVANCE
INFORMATION
• Phase-Lock Loop Clock Distribution
• 10MHz to 133MHz operating frequency
• Distributes one clock input to one bank of five and one bank of
four outputs
• Separate output enable for each output bank
• Output Skew < 250ps
• Low jitter <200 ps cycle-to-cycle
• No external RC network required
• Operates at 2.5V V
DD
• Spread spectrum compatible
• Available in SOIC package
The IDT23S09T is a high-speed phase-lock loop (PLL) clock buffer,
designed to address high-speed clock distribution applications. The zero
delay is achieved by aligning the phase between the incoming clock and
the output clock, operable within the range of 10 to 133MHz.
The IDT23S09T is a 16-pin version of the IDT23S05T. The IDT23S09T
accepts one reference input, and drives two banks of four low skew clocks.
All parts have on-chip PLLs which lock to an input clock on the REF pin.
The PLL feedback is on-chip and is obtained from the CLKOUT pad. In
the absence of an input clock, the IDT23S09T enters power down, and
the outputs are tri-stated. In this mode, the device will draw less than 12µA.
FUNCTIONAL BLOCK DIAGRAM
16
CLKOUT
1
REF
PLL
2
CLKA1
3
CLKA2
14
CLKA3
15
CLKA4
S2
S1
8
9
Control
Logic
6
CLKB1
7
CLKB2
10
CLKB3
11
CLKB4
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
1
c
2003 Integrated Device Technology, Inc.
OCTOBER 2003
DSC 6396/5
IDT23S09T
2.5V ZERO DELAY CLOCK BUFFER, SPREAD SPECTRUM COMPATIBLE
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
REF
CLKA1
CLKA2
V
DD
GND
CLKB1
CLKB2
S2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SOIC
TOP VIEW
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Rating
Supply Voltage Range
Input Voltage Range (REF)
Input Voltage Range
(except REF)
I
IK
(V
I
< 0)
I
O
(V
O
= 0 to V
DD
)
V
DD
or GND
T
A
= 55°C
(in still air)
(3)
T
STG
Operating
Temperature
Storage Temperature Range
Commercial Temperature
Range
–65 to +150
0 to +70
°C
°C
Input Clamp Current
Continuous Output Current
Continuous Current
Maximum Power Dissipation
Max.
–0.5 to +4.6
–0.5 to +5.5
–0.5 to
V
DD
+0.5
–50
±50
±100
0.7
mA
mA
mA
W
Unit
V
V
V
CLKOUT
CLKA4
CLKA3
V
DD
GND
CLKB4
CLKB3
S1
V
DD
V
I (2)
V
I
APPLICATIONS:
•
•
•
•
•
SDRAM
Telecom
Datacom
PC Motherboards/Workstations
Critical Path Delay Designs
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. The input and output negative-voltage ratings may be exceeded if the input and output
clamp-current ratings are observed.
3. The maximum package power dissipation is calculated using a junction temperature
of 150°C and a board trace length of 750 mils.
PIN DESCRIPTION
Pin Name
REF
(1)
CLKA1
(2)
CLKA2
V
DD
GND
CLKB1
(2)
CLKB2
(2)
S2
(3)
S1
(3)
CLKB3
(2)
CLKB4
(2)
(2)
Pin Number
1
2
3
4, 13
5, 12
6
7
8
9
10
11
14
15
16
Type
IN
Out
Out
PWR
GND
Out
Out
IN
IN
Out
Out
Out
Out
Out
Functional Description
Input reference clock, 3.3V tolerant input
Output clock for bank A
Output clock for bank A
2.5V Supply
Ground
Output clock for bank B
Output clock for bank B
Select input Bit 2
Select input Bit 1
Output clock for bank B
Output clock for bank B
Output clock for bank A
Output clock for bank A
Output clock, internal feedback on this pin
CLKA3
(2)
CLKA4
(2)
CLKOUT
(2)
NOTES:
1. Weak pull down.
2. Weak pull down on all outputs.
3. Weak pull ups on these inputs.
2
IDT23S09T
2.5V ZERO DELAY CLOCK BUFFER, SPREAD SPECTRUM COMPATIBLE
COMMERCIAL TEMPERATURE RANGE
FUNCTION TABLE
(1)
S2
L
L
H
H
S1
L
H
L
H
CLKA
Tri-State
Driven
Driven
Driven
CLKB
Tri-State
Tri-State
Driven
Driven
CLKOUT
(2)
Driven
Driven
Driven
Driven
Output Source
PLL
PLL
REF
PLL
PLL Shut Down
N
N
Y
N
NOTES:
1. H = HIGH Voltage Level.
L = LOW Voltage Level
2. This output is driven and has an internal feedback for the PLL. The load on this ouput can be adjusted to change the skew between the REF and the output.
DC ELECTRICAL CHARACTERISTICS
Symbol
V
IL
V
IH
I
IL
I
IH
V
OL
V
OH
I
DD_PD
I
DD
Parameter
Input LOW Voltage Level
Input HIGH Voltage Level
Input LOW Current
Input HIGH Current
Output LOW Voltage
Output HIGH Voltage
Power Down Current
Supply Current
V
IN
= 0V
V
IN
= V
DD
Standard Drive, I
OL
= 8mA
Standard Drive, I
OH
= -8mA
REF = 0MHz (S2 = S1 = H)
Unloaded Outputs at 66.66MHz, SEL inputs at V
DD
or GND
Conditions
Min.
—
1.7
—
—
—
2
—
—
Max.
0.7
—
50
100
0.3
—
12
32
Unit
V
V
µA
µA
V
V
µA
mA
OPERATING CONDITIONS
Symbol
V
DD
T
A
C
L
C
IN
Supply Voltage
Operating Temperature (Ambient Temperature)
Load Capacitance 10MHz - 133MHz
Input Capacitance
Parameter
Min.
2.3
0
—
—
Max.
2.7
70
15
7
Unit
V
°
C
pF
pF
SWITCHING CHARACTERISTICS
Symbol
t
1
t
3
t
4
t
5
t
6A
t
6B
t
7
t
J
t
LOCK
Parameter
Output Frequency
Duty Cycle = t
2
÷
t
1
Rise Time
Fall Time
Output to Output Skew
(1,2)
Conditions
15pF Load
Measured at V
DD
/2, F
OUT
= 66.66MHz
Measured between 0.7V and 1.7V
Measured between 0.7V and 1.7V
All outputs equally loaded
Min.
10
40
—
—
—
—
1
—
—
—
Typ.
—
50
—
—
—
0
5
0
—
—
Max.
133
60
2.5
2.5
250
±350
8.7
700
200
1
Unit
MHz
%
ns
ns
ps
ps
ns
ps
ps
ms
Delay, REF Rising Edge to CLKOUT Rising Edge
(2)
Measured at V
DD
/2
Delay, REF Rising Edge to CLKOUT Rising Edge
(2)
Measured at V
DD
/2 in PLL bypass mode
Device-to-Device Skew
Cycle-to-Cycle Jitter
PLL Lock Time
Measured at V
DD
/2 on the CLKOUT pins of devices
Measured at 66.66MHz, loaded outputs
Stable power supply, valid clock presented on REF pin
NOTES:
1. REF Input has a threshold voltage of V
DD
/2.
2. All parameters specified with loaded outputs.
3
IDT23S09T
2.5V ZERO DELAY CLOCK BUFFER, SPREAD SPECTRUM COMPATIBLE
COMMERCIAL TEMPERATURE RANGE
ZERO DELAY AND SKEW CONTROL
All outputs should be uniformly loaded in order to achieve Zero I/O Delay. Since the CLKOUT pin is the internal feedback for the PLL, its relative
loading can affect and adjust the input/output delay.
For designs utilizing zero I/O Delay, all outputs including CLKOUT must be equally loaded. Even if the output is not used, it must have a capacitive
load equal to that on the other outputs in order to obtain true zero I/O Delay. For zero output-to-output skew, all outputs must be loaded equally.
SPREAD SPECTRUM COMPATIBLE
Many systems being designed now use a technology called Spread Spectrum Frequency Timing Generation. This product is designed not to filter
off the Spread Spectrum feature of the reference input, assuming it exists. When a zero delay buffer is not designed to pass the Spread Spectrum feature
through, the result is a significant amount of tracking skew, which may cause problems in systems requiring synchronization.
4
IDT23S09T
2.5V ZERO DELAY CLOCK BUFFER, SPREAD SPECTRUM COMPATIBLE
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