SC660C
I
2
C System Clock Buffer for Mobile Applications
Approved Product
PRODUCT FEATURES
S
S
S
S
S
S
PRODUCT DESCRIPTION
The device is a high fanout system clock distributor. Its
primary application is to create the large quantity of
clocks needed to support a wide range of clock loads
that are referenced to a single existing clock. Loads of
up to 30 pF are supported. Primary application of this
component is where long traces are used to transport
clocks from their generating devices to their loads. The
creation of EMI and the degradation of waveform rise
and fall times is greatly reduced by running a single
reference clock trace to this device and then using it to
regenerate the clock that drives shorter traces by using
the IMISC660 to generate the clocks at the target
devices EMI is therefore minimized and board real
estate is saved.
10 output buffers for high clock fanout applications
Each output can be internally disabled for EMI and
power consumption reduction.
Separate power supply for each group of 2 clock
outputs for mixed voltage application.
< 250ps skew between output clocks.
28-pin SSOP package for minimum boad space
Single output Tristate pin for testability
BLOCK DIAGRAM
VDDB
CONNECTION DIAGRAM
SDRAM(0:1)
SDRAM(2:3)
SDRAM4
FIN
SDRAM5
VDD
SDATA
SCLOCK
OE
I2C
SDRAM(6:7)
SDRAM(8:9)
VDDB
SDRAM0
SDRAM1
VSS
VDDB
SDRAM2
SDRAM3
VSS
FIN
VDDB
SDRAM4
VSS
VDD
SDATA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDDB
SDRAM9
SDRAM8
VSS
VDDB
SDRAM7
SDRAM6
VSS
OE
VDDB
SDRAM5
VSS
VSS
SCLOCK
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Rev.1.7
8/12/98
Page 1 of 7
SC660C
I
2
C System Clock Buffer for Mobile Applications
Approved Product
PIN DESCRIPTION
PIN
No.
9
2,3,6,7,1
1,18,22,2
3,26,27
20
Pin
Name
FIN
SDRAM(0:9)
PWR
-
VDDB
I/O
I
O
TYPE
PAD
BUF1
Description
This pin is connected to the input reference clock. This clock
must be in the range of 10.0 to 100.0 Mhz.
Low skew output clocks.
OE
-
I
PAD
14
SDATA
VDD
I/O
PAD
15
4, 8, 12,
16, 17,
21, 25
1, 5, 10,
19, 24,
28
13
SCLOCK
VSS
VDD
I
PWR
PAD
-
Buffer Output Enable pin. This pin is low it is used to place
all output clocks (CLK1:10) in a tri state condition. This
feature facilitates in production board level testing to be
easily implemented for the clocks that this device produces.
Has internal pull-up resistor.
Serial Data for I2C control interface. This pin receives data
streeams from the I2C bus and outputs an acknowledge for
valid data.
Serial Clock for I2C control interface.
Ground pins for clock output buffers. These pins must be
returned to the same potential to reduce output clock skew.
Power for output clock buffers.
VDDB
-
PWR
-
VDD
-
PWR
-
Pin for device core logic.
MAXIMUM RATINGS
Voltage Relative to VSS:
Voltage Relative to VDD:
Storage Temperature:
Operating Temperature:
Maximum Power Supply:
-0.3V
0.3V
-65ºC to + 150ºC
-40ºC to +85ºC
7V
This device contains circuitry to protect the inputs
against damage due to high static voltages or electric
field; however, precautions should be taken to avoid
application of any voltage higher than the maximum
rated voltages to this circuit. For proper operation, Vin
and Vout should be constrained to the range:
VSS<(Vin or Vout)<VDD
Unused inputs must always be tied to an appropriate
logic voltage level (either VSS or VDD).
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Rev.1.7
8/12/98
Page 2 of 7
SC660C
I
2
C System Clock Buffer for Mobile Applications
Approved Product
2-WIRE I
2
C CONTROL INTERFACE
The 2-wire control interface implements a write only slave interface. The device cannot be read back. Sub-
addressing is not supported, thus all preceeding bytes must be sent in order to change one of the control bytes. The 2-
wire control interface allows each clock output to be individually enabled or disabled.
During normal data transfer, the SDATA signal only changes when the SDCLK signal is low, and is stable when
SDCLK is high. There are two exceptions to this. A high to low transition on SDATA while SDCLK is high is used to
indicate the start of a data transfer cycle. A low to high transition on SDATA while SDCLK is high indicates the end of a
data transfer cycle. Data is always sent as complete 8-bit bytes, after which an acknowledge is generated. The first
byte of a transfer cycle is a 7-bit address with a Read/Write bit as the LSB. Data is transferred MSB first.
The device will respond to writes to 10 bytes (max) of data to address
D2
by generating the acknowledge (low)
signal on the SDATA wire following reception of each byte. The device will not respond to any other control interface
conditions. Previously set control registers are retained.
SERIAL CONTROL REGISTERS
NOTE:
The Pin# column lists the affected pin number where applicable. The @Pup column gives the state at true
power up. Bytes are set to the values shown only on true power up, and not when the PWR_DWN# pin is activated.
Following the acknowledge of the Address Byte (D2), two additional bytes must be sent:
1) “Command
Code
“ byte, and
2) “Byte
Count”
byte.
Although the data (bits) in these two bytes are considered “don’t care”, they must be sent and will be acknowledged.
After the Command Code and the Count bytes have been acknowledged, the below desrcibed sequence (Byte
0, Byte 1, Byte2, ....) will be valid and acknowledged.
Byte 0: Function Select Register(1
= enable, 0 = Stopped)
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
1
1
1
1
1
1
Pin#
-
-
-
-
7
6
3
2
Description
reserved
reserved
reserved
reserved
SDRAM3 (Active = 1, Forced low = 0)
SDRAM2 (Active = 1, Forced low = 0)
SDRAM1 (Active = 1, Forced low = 0)
SDRAM0 (Active = 1, Forced low = 0)
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Rev.1.7
8/12/98
Page 3 of 7
SC660C
I
2
C System Clock Buffer for Mobile Applications
Approved Product
SERIAL CONTROL REGISTERS (Cont.)
Byte 1: Clock Register
(1 = enable, 0 = Stopped)
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
1
1
1
1
1
1
Pin#
27
26
23
22
-
-
-
-
Description
SDRAM9 (Active = 1, Forced low = 0)
SDRAM8 (Active = 1, Forced low = 0)
SDRAM7 (Active = 1, Forced low = 0)
SDRAM6 (Active = 1, Forced low = 0)
reserved
reserved
reserved
reserved
Byte 4: Clock Register
( 1 = enable, 0 = Stopped )
Bit
7
6
5
4
3
2
1
0
@Pup
0
0
0
0
0
0
1
1
Pin#
18
11
-
-
-
-
-
-
Description
SDRAM5 (Active = 1, Forced low = 0)
SDRAM4 (Active = 1, Forced low = 0)
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Rev.1.7
8/12/98
Page 4 of 7
SC660C
I
2
C System Clock Buffer for Mobile Applications
Approved Product
ELECTRICAL CHARACTERISTICS
Characteristic
Input Low Voltage
Input High Voltage
Input Low Current
Input High Current
Output Low Voltage
IOL = 4mA
Output High Voltage
IOH = 4mA
Tri-State leakage Current
Dynamic Supply Current
Idd
100
Static Supply Current
Short Circuit Current
Input Rise Time
Isdd
ISC
TIR
-
-
25
2.4
-
-
-
-
220
4
-
-
mA
mA
mA
nS
Symbol
VIL
VIH
IIL
IIH
VOL
VOH
Ioz
Idd
66
-
2.4
-
-
-
-
-
-
Min
-
2.0
-66
66
0.4
-
10
160
Typ
-
-
Max
0.8
-
Units
Vdc
Vdc
µA
µA
Vdc
Vdc
µA
mA
Input frequency = 66 Mhz - All outputs on
and at 30 pF load
Input frequency 100 Mhz - All outputs on
and at 30 pF load
All outputs disabled no input clock
1 output at a time - 30 seconds
.8 to 2.4 volts
All Outputs (see buffer spec)
All Outputs Using 3.3V Power
(see buffer spec)
Conditions
-
-
VDD = VDD1 thru VDD5 =3.3V
±5
%, , TA = -40ºC to +85ºC
SWITCHING CHARACTERISTICS
Characteristic
Output Duty Cycle
Buffer out/out Skew All
Buffer Outputs
Buffer input to output Skew
Jitter Cycle to Cycle*
Jitter Absolute (Peak to
Peak)*
Symbol
-
tSKEW
tSKEW
TJCC
TJabs
Min
45
-
2.0
Typ
50
-
4.0
Max
55
250
5.0
50
150
Units
%
pS
nS
pS
pS
@ 35 pF loading
@ 35 pF loading
Conditions
Measured at 1.5V (50/50 in)
35 pF Load Measured at 1.5V
VDD = VDD1 thru VDD5 = 3.3V
±5
%, , TA = -40ºC to +85ºC
*This jitter is additive to the input clock’s jitter.
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Rev.1.7
8/12/98
Page 5 of 7
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