Model 653
LVPECL or LVDS Clock Oscillator
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FEATURES
Standard 5.0mm x 3.2mm 6-Pad Surface Mount Package
Low Phase Jitter, 0.7ps RMS Maximum
LVPECL or LVDS Output
Fundamental and 3
rd
Overtone Crystal Designs
Frequency Range 25 – 320 MHz
Frequency Stability ±50 ppm Standard
Operating Voltages +2.5Vdc or +3.3Vdc
Operating Temperature to -40°C to +85°C
Output Enable Standard
Tape & Reel Packaging Standard, EIA-418
RoHS/Green Compliant [6/6]
APPLICATIONS
Model 653 is ideal for applications such as broadband access, Ethernet/Gigabit Ethernet, SONET/SDH and
optical networking.
ORDERING INFORMATION
653
OUTPUT TYPE
P = LVPECL - Pin 1 Enable [std]
L = LVDS - Pin 1 Enable [std]
E = LVPECL - Pin 2 Enable [opt]
V = LVDS - Pin 2 Enable [opt]
FREQUENCY
Product Frequency Code
1
PACKAGING
T - 1k pcs./reel
SUPPLY VOLTAGE
2 = 2.5 Vdc
3 = 3.3 Vdc
OPERATING TEMPERATURE RANGE
A = -10°C to +60°C
C = -20°C to +70°C
2
I = -40°C to +85°C
FREQUENCY STABILITY
6 = ± 20 ppm
5 = ± 25 ppm
3 = ± 50 ppm
2
1] Refer to document 016-1454-0, Frequency Code Tables.
3-digits required for frequencies below 100MHz and 4-digits for frequencies 100MHz or greater.
2] Consult factory for availability of 6I Stability/Temperature combination.
Not all performance combinations and frequencies may be available.
Contact your local CTS Representative or CTS Customer Service for availability.
PACKAGING INFORMATION
[reference]
Device quantity is 1k pcs. maximum per 180mm reel.
Document No. 008-0367-0
Page 1- 3
Rev. A
www.ctscorp.com
Model 653
5.0mm x 3.2mm Low Jitter
LVPECL or LVDS Clock Oscillator
ELECTRICAL CHARACTERISTICS
PARAMETER
Maximum Supply Voltage
Storage Temperature
Frequency Range
LVPECL
LVDS
Frequency Stability
Operating Temperature
Commercial
Industrial
Supply Voltage
Supply Current
LVPECL
LVDS
Start Up Time
T
S
tjrms
pjrms
Standby
V
IH
V
IL
T
PLZ
T
PLZ
R
L
SYM
V
OH
V
OL
V
OH
V
OL
T
R
, T
F
R
L
SYM
V
OD
V
OS
V
OH
V
OL
T
R
, T
F
Pin 1 or 2 Logic '1', Output Enabled
Pin 1 or 2 Logic '0', Output Disabled
Pin 1 or 2 Logic '0' , Output Disabled
Pin 1 or 2 Logic '1', Output Enabled
Terminated to V
CC
- 2.0V
@ V
CC
- 1.3V
PECL Load, -20°C to +70°C
PECL Load, -20°C to +70°C
PECL Load, -40°C to +85°C
PECL Load, -40°C to +85°C
@ 20% - 80% Levels
Between Outputs
@ 1.25V
R
L
= 100 Ohms
LVDS Load
LVDS Load
LVDS Load
@ 20% - 80% Levels
0.7*V
CC
-
-
-
-
45
V
CC
- 1.025
V
CC
- 1.810
V
CC
- 1.085
V
CC
- 1.830
-
-
45
247
1.125
-
0.9
-
-
-
-
-
50
-
-
-
-
-
0.6
100
-
350
1.25
1.43
1.1
0.4
-
0.3*V
CC
200
2
-
55
V
CC
- 0.880
V
CC
- 1.620
V
CC
- 0.880
V
CC
- 1.555
1.0
-
55
454
1.375
1.6
-
0.7
ns
ns
ms
Ohms
%
V
Application of V
CC
Bandwidth 12 kHz - 20 MHz
-
-
I
CC
Maximum Load
-
-
-
-
-
-
-
-
2
0.3
2.6
25
88
65
5
0.7
-
-
ps
ms
mA
T
A
-
-20
-40
V
CC
±5%
2.38
3.14
25
2.5
3.3
+70
+85
2.63
3.47
V
°C
f
O
-
All Inclusive, see Note 1.
1st year aging
25
80
Δf/f
O
-
-
-
-
-
-
320
320
20, 25, 50
3
± ppm
MHz
SYMBOL
V
CC
T
STG
CONDITIONS
-
-
MIN
-0.5
-40
TYP
-
-
MAX
5.0
+100
UNIT
V
°C
ELECTRICAL PARAMETERS
Phase Jitter
Period Jitter RMS
Period Jitter Pk-Pk
Enable Function
Enable Input Voltage
Disable Input Voltage
Disable Time
Enable Time
LVPECL WAVEFORM
Output Load
Output Duty Cycle
Output Voltage Levels
Logic '1' Level
Logic '0' Level
Logic '1' Level
Logic '0' Level
Rise and Fall Time
LVDS WAVEFORM
Output Load
Output Duty Cycle
Differential Output Voltage
Offset Voltage
Output Voltage Levels
Logic '1' Level
Logic '0' Level
Rise and Fall Time
V
V
ns
Ohms
%
mV
V
V
Notes:
1. Inclusive of initial tolerance at time of shipment, changes in supply voltage, load, temperature and 1st year aging.
LVPECL/LVDS OUTPUT WAVEFORM
ENABLE TRUTH TABLE
PIN 1 or Pin 2
Logic ‘1’
Open
Logic ‘0’
PIN 4 & 5
Output
Output
High Imp.
Document No. 008-0367-0
Page 2 - 3
Rev. A
Model 653
5.0mm x 3.2mm Low Jitter
LVPECL or LVDS Clock Oscillator
TEST CIRCUIT, LVPECL LOAD
TEST CIRCUIT, LVDS LOAD
MECHANICAL SPECIFICATIONS
PACKAGE DRAWING
MARKING INFORMATION
1. ** - Manufacturing Site Code.
2. D – Date Code. See Table I for codes.
3. O – Output Type. P or E = LVPECL, L or V = LVDS.
[Refer to Ordering Information.]
CTS**D
653OSTV
●
xxxx
4. ST – Frequency stability/temperature code.
5. V – Voltage code. 3 = 3.3V, 2 = 2.5V
6. xxxx – Frequency Code.
3-digits, frequencies below 100MHz
4-digits, frequencies 100MHz or greater.
Refer to document 016-1454-0, Frequency Code Tables.
[Refer to Ordering Information.]
SUGGESTED SOLDER PAD GEOMETRY
C
BYPASS
should be
≥
0.01 uF.
NOTES
1. Complete CTS part number, frequency value and
date code information must appear on reel and
carton labels.
2. Termination pads [e4]. Barrier-plating is nickel [Ni]
with gold [Au] flash plate.
3. Reflow conditions per JEDEC J-STD-020; 260°C
maximum, 20 seconds.
4. MSL = 1.
D.U.T. PIN ASSIGNMENTS
PIN
SYMBOL
1
2
3
4
5
6
EOH or N.C.
N.C. or EOH
GND
Output
Output
V
CC
DESCRIPTION
Enable [std] or No Connect
No Connect or Enable [opt]
Circuit & Package Ground
RF Output
Complimentary RF Output
Supply Voltage
TABLE I – DATE CODE
MONTH
YEAR
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
JAN
A
N
a
n
FEB
B
P
b
p
MAR
C
Q
c
q
APR
D
R
d
r
MAY
E
S
e
s
JUN
F
T
f
t
JUL
G
U
g
u
AUG
H
V
h
v
SEP
J
W
j
w
OCT
K
X
k
x
NOV
L
Y
l
y
DEC
M
Z
m
z
Document No. 008-0367-0
Page 3 - 3
Rev. A
FPGA/CPLD
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