.
IBM13M64734HCA
64M x 72 Two-Bank Registered SDRAM Module
Features
• 168-Pin Registered 8-Byte Dual In-Line Memory
Module
• 64Mx72 Synchronous DRAM DIMM
• Performance:
DIMM CAS Latency
f
CK
Clock Frequency
f
CK
Clock Cycle
t
AC
Clock Access
-75A
4
133
100
7.5
10
5.65
5.65
Units
MHz
ns
ns
•
•
•
•
•
•
•
Intended for 100MHz and 133MHz applications
Inputs and outputs are LVTTL (3.3V) compatible
Single 3.3V
±
0.3V Power Supply
Single Pulsed RAS interface
SDRAMs have four internal banks
Module has two physical banks
Fully Synchronous to positive Clock Edge
• Programmable Operation:
- DIMM CAS Latency: 3, 4 (Registered mode)
- Burst Type: Sequential or Interleave
- Burst Length: 1, 2, 4, 8
- Operation: Burst Read and Write or Multiple
Burst Read with Single Write
• Data Mask for Byte Read/Write control
• Auto Refresh (CBR) and Self Refresh
• Automatic and controlled Precharge Commands
• Suspend Mode and Power Down Mode
• 13/10/2 Addressing (Row/Column/Bank)
• 8192 refresh cycles distributed across 64ms
• Card size: 5.25" x 0.157" x 1.70"
• Gold contacts
• SDRAMs in TSOP
• Serial Presence Detect with Write protect
Description
IBM13M64734HCA is a registered 168-Pin Synchro-
nous DRAM Dual In-Line Memory Module (DIMM)
organized as a 64Mx72 high-speed memory array
and is configured as two 32M x 72 physical banks.
The DIMM uses eighteen 32Mx8 SDRAMs in 400
mil TSOP packages. The DIMM achieves high-
speed data-transfer rates of 100MHz and 133MHz
by employing a prefetch/pipeline hybrid architecture
that synchronizes the output data to a system clock.
The DIMM is intended for use in applications operat-
ing at 100MHz and 133MHz memory bus speeds. All
control and address signals are re-driven through
registers to the SDRAM devices. The DIMM oper-
ates in registered mode (REGE pin tied high), during
which the control/address input signals are latched
in the register on one rising clock edge and sent to
the SDRAM devices on the following rising clock
edge (data access is delayed by one clock).
A phase-lock loop (PLL) on-board the DIMM re-
drives the clock signals to the SDRAM devices and
registers to minimize system clock loading. (CK0 is
connected to the PLL, and CK1, CK2, and CK3 are
terminated on the DIMM.) A single clock enable
(CKE0) controls all devices on the DIMM, enabling
the use of SDRAM power-down modes.
Prior to any access operation, the device CAS
latency and burst type/length/operation type must be
programmed into the DIMM by address inputs A0-A9
using the mode register set cycle. The DIMM CAS
latency is one clock later due to the address and
control signals being clocked to the SDRAM
devices.
The DIMM uses serial presence detects imple-
mented via a serial EEPROM using the two-pin IIC
protocol. The first 128 bytes of serial PD data are
programmed and locked by the DIMM manufacturer.
The last 128 bytes are available to the customer and
can be write protected by providing a high level to
pin 81 on the DIMM. An on-board pulldown resistor
keeps this in the write-enable mode.
All IBM 168-pin DIMMs provide a high-performance,
flexible 8-byte interface in a 5.25" long space-saving
footprint.
06K8049.H03530
5/00
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 1 of 22
IBM13M64734HCA
64M x 72 Two-Bank Registered SDRAM Module
Card Outline
(Front)
(Back)
1
85
10 11
94 95
40
124
41
125
84
168
Pin Description
CK0-CK3
CKE0
RAS
CAS
WE
S0, S1, S2, S3
A0-A9, A11, A12
A10/AP
BA0, BA1
WP
Clock Inputs
Clock Enable
Row Address Strobe
Column Address Strobe
Write Enable
Chip Selects
Address Inputs
Address Input/Autoprecharge
SDRAM Bank Address Inputs
SPD Write Protect
DQ0 - DQ63
CB0 - CB7
DQMB0 - DQMB7
V
DD
V
SS
NC
SCL
SDA
SA0-2
REGE
Data Input/Output
Check Bit Data Input/Output
Data Mask
Power (3.3V)
Ground
No Connect
Serial Presence Detect Clock Input
Serial Presence Detect Data
Input/Output
Serial Presence Detect Address
Inputs
Register Enable
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
06K8049.H03530
5/00
Page 2 of 22
IBM13M64734HCA
64M x 72 Two-Bank Registered SDRAM Module
Pinout
Pin#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Front
Side
V
SS
DQ0
DQ1
DQ2
DQ3
V
DD
DQ4
DQ5
DQ6
DQ7
DQ8
V
SS
DQ9
DQ10
DQ11
DQ12
DQ13
V
DD
DQ14
DQ15
CB0
Pin#
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
Back
Side
V
SS
DQ32
DQ33
DQ34
DQ35
V
DD
DQ36
DQ37
DQ38
DQ39
DQ40
V
SS
DQ41
DQ42
DQ43
DQ44
DQ45
V
DD
DQ46
DQ47
CB4
Pin#
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
Front
Side
CB1
V
SS
NC
NC
V
DD
WE
DQMB0
DQMB1
S0
NC
V
SS
A0
A2
A4
A6
A8
A10/AP
BA1
V
DD
V
DD
CK0
Pin#
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
Back
Side
CB5
V
SS
NC
NC
V
DD
CAS
DQMB4
DQMB5
S1
RAS
V
SS
A1
A3
A5
A7
A9
BA0
A11
V
DD
CK1
A12
Pin#
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
Front
Side
V
SS
NC
S2
DQMB2
DQMB3
NC
V
DD
NC
NC
CB2
CB3
V
SS
DQ16
DQ17
DQ18
DQ19
V
DD
DQ20
NC
NC
NC
Pin#
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
Back
Side
V
SS
CKE0
S3
DQMB6
DQMB7
NC
V
DD
NC
NC
CB6
CB7
V
SS
DQ48
DQ49
DQ50
DQ51
V
DD
DQ52
NC
NC
REGE
Pin#
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Front
Side
V
SS
DQ21
DQ22
DQ23
V
SS
DQ24
DQ25
DQ26
DQ27
V
DD
DQ28
DQ29
DQ30
DQ31
V
SS
CK2
NC
WP
SDA
SCL
V
DD
Pin#
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
Back
Side
V
SS
DQ53
DQ54
DQ55
V
SS
DQ56
DQ57
DQ58
DQ59
V
DD
DQ60
DQ61
DQ62
DQ63
V
SS
CK3
NC
SA0
SA1
SA2
V
DD
Note:
All pin assignments are consistent with all 8-byte unbuffered versions.
Ordering Information
Part Number
IBM13M64734HCA-75AT
Organization
64Mx72
Clock Cycle
(CL, t
RCD
,
t
P
)
7.5ns (3,3,3)
Device Access
Time
5.65ns
Leads
Gold
Dimension
5.25" x 0.157" x 1.70"
Power
3.3V
06K8049.H03530
5/00
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 3 of 22
IBM13M64734HCA
64M x 72 Two-Bank Registered SDRAM Module
64Mx72 SDRAM DIMM Block Diagram
RS1
RS0
DQMB0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
(2 Bank, 32Mx8 SDRAMs)
DQMB4
*
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
D0
D9
D5
D14
DQMB1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQMB5
D1
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
D10
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
D6
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
D15
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQM
D2
D11
DQMB6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
D7
RS3
RS2
DQMB2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
D16
D3
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
D12
DQMB7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
D8
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
D17
DQMB3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
D4
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
Note: Exact DQ wiring may differ from that shown above.
#
Unless otherwise noted, resistor values are 10 Ohms.
Serial Presence Detect
SCL
WP
47K
SDA
A0
SA0
V
DD
V
SS
A1
SA1
A2
SA2
D0 - D17
D0 - D17
PLL
CK0
CK1, CK2, CK3 Terminated
D13
S0-S3
DQMB0 to DQMB7
BA0-BA1
A0-A12
RAS
CAS
CKE0
WE
10k
V
DD
REGE
PCK
R
E
G
I
S
T
E
R
RS0-RS3
RDQMB0 - RDQMB7
BS0-BS1: SDRAMs D0-D17
RBA0 - RBA1
A0-A12: SDRAMs D0-D17
RA0-RA12
RRAS
RAS: SDRAMs D0 - D17
CAS: SDRAMs D0 - D17
RCAS
CKE: SDRAMs D0 - D17
RCKE0
RWE
WE: SDRAMs D0 - D17
Note: DQ wiring may differ from that described
in this drawing; however, DQ/DQMB
relationships are maintained as shown.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
06K8049.H03530
5/00
Page 4 of 22
IBM13M64734HCA
64M x 72 Two-Bank Registered SDRAM Module
Input/Output Functional Description
Symbol
CK0 - CK3
Type
Input
Signal
Pulse
Polarity
Positive
Edge
Function
The system clock inputs. All the SDRAM inputs are sampled on the rising edge of
their associated clock. CK0 drives the PLL. CK1, CK2, and CK3 are terminated.
CKE0
Input
Level
Activates the SDRAM CK signal when high and deactivates the CK signal when low.
Active High By deactivating the clocks, CKE low initiates the Power Down mode, the Suspend
mode, or the Self Refresh mode.
Active Low
Enables the associated SDRAM command decoder when low and disables the com-
mand decoder when high. When the command decoder is disabled, new commands
are ignored but previous operations continue.
When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the
operation to be executed by the SDRAM.
Selects which SDRAM bank of four is activated.
During a Bank Activate command cycle, A0-A12 defines the row address (RA0-
RA12) when sampled at the rising clock edge.
During a Read or Write command cycle, A0-A9 define the column address (CA0-
CA9) when sampled at the rising clock edge. In addition to the column address, AP is
used to invoke autoprecharge operation at the end of the burst read or write cycle. If
AP is high, autoprecharge is selected and BA0, BA1 defines the bank to be pre-
charged. If AP is low, autoprecharge is disabled.
During a Precharge command cycle, AP is used in conjunction with BA0, BA1 to con-
trol which bank(s) to precharge. If AP is high, all banks will be precharged regardless
of the state of BA0 or BA1. If AP is low, BA0 and BA1 are used to define which bank
to precharge.
Data and Check Bit Input/Output pins.
S0-S3
RAS, CAS
WE
BA0, 1
Input
Pulse
Input
Input
Pulse
Level
Active Low
—
A0 - A9
A10/AP
A11, A12
Input
Level
—
DQ0 - DQ63,
CB0 - CB7
Input
Output
Level
—
DQMB0 -
DQMB7
Input
Pulse
The Data Input/Output masks, associated with one data byte, place the DQ buffers in
a high-impedance state when sampled high. In Read mode, DQMB has a latency of
two clock cycles in Buffered mode or three clock cycles in Registered mode, and con-
Active High trols the output buffers like an output enable.
In Write mode, DQMB has a zero clock latency in Buffered mode and a latency of
one clock cycle in Registered mode. In this case, DQMB operates as a byte mask by
allowing input data to be written if it is low but blocking the write operation if it is high.
—
Power and ground for the module.
V
DD
, V
SS
Supply
REGE
Input
Level
Active High
(Register The Register Enable pin must be held high to permit the DIMM to operate in “regis-
tered” mode (signals re-driven to SDRAMs when clock rises, and held valid until next
Mode
rising clock).
Enable)
—
—
—
These signals are tied at the system planar to either V
SS
or V
DD
to configure the
serial SPD EEPROM.
This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A
resistor must be connected from the SDA bus line to V
DD
to act as a pullup.
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be
connected from the SCL bus time to V
DD
to act as a pullup.
SA0 - 2
SDA
SCL
WP
Input
Input
Output
Input
Input
Level
Level
Pulse
Level
Active High This signal is pulled low on the DIMM to enable data to be written into the last 128
bytes of the SPD EEPROM.
06K8049.H03530
5/00
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 5 of 22
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