IS61VPD51236-200TQI datasheet, PDF

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IS61VPD51236-200TQI: DescriptionCache SRAM, 512KX36, 3.1ns, CMOS, PQFP100, TQFP-100; Categorystorage storage; File Size163KB，24 Pages; ManufacturerIntegrated Silicon Solution ( ISSI )

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IS61VPD51236-200TQI Overview

Cache SRAM, 512KX36, 3.1ns, CMOS, PQFP100, TQFP-100

IS61VPD51236-200TQI Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Integrated Silicon Solution ( ISSI )
Parts packaging code	QFP
package instruction	TQFP-100
Contacts	100
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Maximum access time	3.1 ns
JESD-30 code	R-PQFP-G100
JESD-609 code	e0
length	20 mm
memory density	18874368 bit
Memory IC Type	CACHE SRAM
memory width	36
Number of functions	1
Number of terminals	100
word count	524288 words
character code	512000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	512KX36
Package body material	PLASTIC/EPOXY
encapsulated code	LQFP
Package shape	RECTANGULAR
Package form	FLATPACK, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	240
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum supply voltage (Vsup)	2.625 V
Minimum supply voltage (Vsup)	2.375 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	14 mm

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IS61VPD51232

IS61VPD51236

IS61VPD10018

512K x 32, 512K x 36, 1024K x 18

SYNCHRONOUS PIPELINED,

DOUBLE CYCLE DESELECT STATIC RAM

FEATURES

• Internal self-timed write cycle

• Individual Byte Write Control and Global Write

• Clock controlled, registered address, data and

control

• Linear burst sequence control using MODE input

• Three chip enable option for simple depth expansion

and address pipelining

• Common data inputs and data outputs

• JEDEC 100-Pin TQFP and

119-pin PBGA package

• Single +2.5V, ±5% operation

• Auto Power-down during deselect

• Double cycle deselect

• Snooze MODE for reduced-power standby

• JTAG Boundary Scan for PBGA package

ISSI

ADVANCE INFORMATION

MAY 2001

DESCRIPTION

The

ISSI

IS61VPD51232, IS61VPD51236, and

IS61VPD10018 are high-speed, low-power synchronous

static RAMs designed to provide burstable, high-performance

memory for communication and networking applications.

The IS61VPD51232 is organized as 524,288 words by 32 bits

and the IS61VPD51236 is organized as 524,288 words by

36 bits. The IS61VPD10018 is organized as 1,048,576

words by 18 bits. Fabricated with

ISSI

's advanced CMOS

technology, the device integrates a 2-bit burst counter,

high-speed SRAM core, and high-drive capability outputs

into a single monolithic circuit. All synchronous inputs

pass through registers controlled by a positive-edge-

triggered single clock input.

Write cycles are internally self-timed and are initiated by

the rising edge of the clock input. Write cycles can be one

to four bytes wide as controlled by the write control inputs.

Separate byte enables allow individual bytes to be written.

Byte write operation is performed by using byte write

enable (BWE).input combined with one or more individual

byte write signals (BWx). In addition, Global Write (GW)

is available for writing all bytes at one time, regardless of

the byte write controls.

Bursts can be initiated with either

ADSP

(Address Status

Processor) or

ADSC

(Address Status Cache Controller)

input pins. Subsequent burst addresses can be generated

internally and controlled by the

ADV

(burst address

advance) input pin.

The mode pin is used to select the burst sequence order,

Linear burst is achieved when this pin is tied LOW.

Interleave burst is achieved when this pin is tied HIGH or

left floating.

FAST ACCESS TIME

Symbol

Parameter

Clock Access Time

Cycle Time

Frequency

-200

3.1

200

-166

3.5

166

Units

MHz

This document contains ADVANCE INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best

Integrated Silicon Solution, Inc. — 1-800-379-4774

ADVANCE INFORMATION

05/31/01

Rev. 00A

IS61VPD51236-200TQI Related Products

	IS61VPD51236-200TQI	IS61VPD51232-200TQI	IS61VPD10018-200TQ	IS61VPD51236-166B	IS61VPD51236-166TQ	IS61VPD10018-166TQ	IS61VPD51232-200TQ	IS61VPD10018-200BI
Description	Cache SRAM, 512KX36, 3.1ns, CMOS, PQFP100, TQFP-100	Cache SRAM, 512KX32, 3.1ns, CMOS, PQFP100, TQFP-100	Cache SRAM, 1MX18, 3.1ns, CMOS, PQFP100, TQFP-100	Cache SRAM, 512KX36, 3.5ns, CMOS, PBGA119, PLASTIC, BGA-119	Cache SRAM, 512KX36, 3.5ns, CMOS, PQFP100, TQFP-100	Cache SRAM, 1MX18, 3.5ns, CMOS, PQFP100, TQFP-100	Cache SRAM, 512KX32, 3.1ns, CMOS, PQFP100, TQFP-100	Cache SRAM, 1MX18, 3.1ns, CMOS, PBGA119, PLASTIC, BGA-119
Is it lead-free?	Contains lead	Contains lead	Contains lead	Contains lead	Contains lead	Contains lead	Contains lead	Contains lead
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible
Parts packaging code	QFP	QFP	QFP	BGA	QFP	QFP	QFP	BGA
package instruction	TQFP-100	TQFP-100	TQFP-100	PLASTIC, BGA-119	TQFP-100	TQFP-100	TQFP-100	PLASTIC, BGA-119
Contacts	100	100	100	119	100	100	100	119
Reach Compliance Code	compliant	compliant	compliant	compliant	compliant	compli	compli	compli
ECCN code	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A
Maximum access time	3.1 ns	3.1 ns	3.1 ns	3.5 ns	3.5 ns	3.5 ns	3.1 ns	3.1 ns
JESD-30 code	R-PQFP-G100	R-PQFP-G100	R-PQFP-G100	R-PBGA-B119	R-PQFP-G100	R-PQFP-G100	R-PQFP-G100	R-PBGA-B119
JESD-609 code	e0	e0	e0	e0	e0	e0	e0	e0
length	20 mm	20 mm	20 mm	22 mm	20 mm	20 mm	20 mm	22 mm
memory density	18874368 bit	16777216 bit	18874368 bit	18874368 bit	18874368 bit	18874368 bi	16777216 bi	18874368 bi
Memory IC Type	CACHE SRAM	CACHE SRAM	CACHE SRAM	CACHE SRAM	CACHE SRAM	CACHE SRAM	CACHE SRAM	CACHE SRAM
memory width	36	32	18	36	36	18	32	18
Number of functions	1	1	1	1	1	1	1	1
Number of terminals	100	100	100	119	100	100	100	119
word count	524288 words	524288 words	1048576 words	524288 words	524288 words	1048576 words	524288 words	1048576 words
character code	512000	512000	1000000	512000	512000	1000000	512000	1000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	85 °C	85 °C	70 °C	70 °C	70 °C	70 °C	70 °C	85 °C
organize	512KX36	512KX32	1MX18	512KX36	512KX36	1MX18	512KX32	1MX18
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LQFP	LQFP	LQFP	BGA	LQFP	LQFP	LQFP	BGA
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	GRID ARRAY	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	GRID ARRAY
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
Peak Reflow Temperature (Celsius)	240	240	240	240	240	240	240	240
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.6 mm	1.6 mm	1.6 mm	2.41 mm	1.6 mm	1.6 mm	1.6 mm	2.41 mm
Maximum supply voltage (Vsup)	2.625 V	2.625 V	2.625 V	2.625 V	2.625 V	2.625 V	2.625 V	2.625 V
Minimum supply voltage (Vsup)	2.375 V	2.375 V	2.375 V	2.375 V	2.375 V	2.375 V	2.375 V	2.375 V
Nominal supply voltage (Vsup)	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V
surface mount	YES	YES	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	GULL WING	GULL WING	GULL WING	BALL	GULL WING	GULL WING	GULL WING	BALL
Terminal pitch	0.65 mm	0.65 mm	0.65 mm	1.27 mm	0.65 mm	0.65 mm	0.65 mm	1.27 mm
Terminal location	QUAD	QUAD	QUAD	BOTTOM	QUAD	QUAD	QUAD	BOTTOM
Maximum time at peak reflow temperature	30	30	30	30	30	30	30	30
width	14 mm	14 mm	14 mm	14 mm	14 mm	14 mm	14 mm	14 mm
Maker	Integrated Silicon Solution ( ISSI )	Integrated Silicon Solution ( ISSI )	-	-	-	Integrated Silicon Solution ( ISSI )	Integrated Silicon Solution ( ISSI )	Integrated Silicon Solution ( ISSI )

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