EEWORLDEEWORLDEEWORLD

Part Number

Search

531QB843M000DGR

Description
CMOS/TTL Output Clock Oscillator, 843MHz Nom, ROHS COMPLIANT, SMD, 6 PIN
CategoryPassive components    oscillator   
File Size215KB,12 Pages
ManufacturerSilicon Laboratories Inc
Environmental Compliance  
Download Datasheet Parametric View All

531QB843M000DGR Overview

CMOS/TTL Output Clock Oscillator, 843MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

531QB843M000DGR Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerSilicon Laboratories Inc
Reach Compliance Codeunknown
Other featuresTAPE AND REEL
maximum descent time0.35 ns
Frequency Adjustment - MechanicalNO
frequency stability20%
JESD-609 codee4
Manufacturer's serial number531
Installation featuresSURFACE MOUNT
Nominal operating frequency843 MHz
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Oscillator typeCMOS/TTL
physical size7.0mm x 5.0mm x 1.85mm
longest rise time0.35 ns
Maximum supply voltage3.63 V
Minimum supply voltage2.97 V
Nominal supply voltage3.3 V
surface mountYES
maximum symmetry55/45 %
Terminal surfaceNickel/Gold (Ni/Au)
S i 5 3 0 / 5 31
R
EVISION
D
C
R Y S TA L
O
S C I L L A T O R
(XO)
(10 M H
Z T O
1.4 G H
Z
)
Features
Available with any-rate output
frequencies from 10 MHz to 945 MHz
and select frequencies to 1.4 GHz
3rd generation DSPLL
®
with superior
jitter performance
3x better frequency stability than
SAW-based oscillators
Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
Si5602
Ordering Information:
See page 7.
Applications
SONET/SDH
Networking
SD/HD video
Test and measurement
Clock and data recovery
FPGA/ASIC clock generation
Pin Assignments:
See page 6.
(Top View)
NC
OE
GND
1
2
3
6
5
4
V
DD
Description
The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry
to provide a low jitter clock at high frequencies. The Si530/531 is available
with any-rate output frequency from 10 to 945 MHz and select frequencies to
1400 MHz. Unlike a traditional XO, where a different crystal is required for
each output frequency, the Si530/531 uses one fixed crystal to provide a
wide range of output frequencies. This IC based approach allows the crystal
resonator to provide exceptional frequency stability and reliability. In addition,
DSPLL clock synthesis provides superior supply noise rejection, simplifying
the task of generating low jitter clocks in noisy environments typically found in
communication systems. The Si530/531 IC based XO is factory configurable
for a wide variety of user specifications including frequency, supply voltage,
output format, and temperature stability. Specific configurations are factory
programmed at time of shipment, thereby eliminating long lead times
associated with custom oscillators.
®
CLK–
CLK+
Si530 (LVDS/LVPECL/CML)
OE
NC
GND
1
2
3
6
5
4
V
DD
Functional Block Diagram
V
DD
CLK– CLK+
NC
CLK
Si530 (CMOS)
Fixed
Frequency
XO
Any-rate
10–1400 MHz
DSPLL
®
Clock
Synthesis
OE
NC
GND
1
2
3
6
5
4
V
DD
CLK–
CLK+
Si531 (LVDS/LVPECL/CML)
OE
GND
Rev. 1.1 6/07
Copyright © 2007 by Silicon Laboratories
Si530/531
MSP430F149
1. Can anyone give me a detailed Chinese pin function diagram of MSP430F149? 2. I am trying to write SVS voltage monitoring, but when I compile it on IAR, it always prompts that the SVSCTL control reg...
zhangya0916 Microcontroller MCU
CAN bus and its application technology
1 Introduction to CAN bus and its characteristicsCAN network (Controller Area Network) is a type of fieldbus technology. It is a new generation of network communication protocol with an open architect...
frozenviolet Automotive Electronics
Industrial Internet of Things (IIoT) Design Resource Center
[size=5]Click to enter>>[url=http://bsch.serving-sys.com/BurstingPipe/adServer.bs?cn=brd&Page=&PluID=56& Pos=7592159931431728&EyeblasterID=28097776&clk=0&sct=1&dg=6462687&di=0&pc=&sessionid=7213277559...
EEWORLD社区 Integrated technical exchanges
Has anyone used INTEL's compiler to compile the Linux kernel?
I found a patch on the Internet, which can compile it, but there are warnings when starting it and it is very slow. Does anyone have any experience?...
tanrui8765 Linux and Android
One of the state machine functions
CPLD, FPGA, these devices, in the general applications I know, such as address decoding, timing conversion, etc., often appear with the port expansion of DSP or ARM, and DSP and ARM often access CPLD,...
lvben5d FPGA/CPLD
Very simple electronic production
I haven't tried it yet! Here are a few forums for learning computer knowledge! I hope you can follow and share learning resources! Deepin Technology Forum System Home Dragon Alliance Forum Kaka Commun...
hzwmz Embedded System

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 1466  1445  417  2647  1830  30  9  54  37  31 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号