70V05L35JG datasheet, PDF - EEWORLD Datasheet

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70V05L35JG: DescriptionDual-Port SRAM, 8KX8, 35ns, CMOS, PQCC68, 0.950 X 0.950 INCH, 0.170 INCH HEIGHT, GREEN, PLASTIC, LCC-68; Categorystorage storage; File Size163KB，22 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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70V05L35JG Overview

Dual-Port SRAM, 8KX8, 35ns, CMOS, PQCC68, 0.950 X 0.950 INCH, 0.170 INCH HEIGHT, GREEN, PLASTIC, LCC-68

70V05L35JG Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
Parts packaging code	LCC
package instruction	QCCN, LDCC68,1.0SQ
Contacts	68
Reach Compliance Code	compliant
ECCN code	EAR99
Maximum access time	35 ns
Other features	INTERRUPT FLAG; SEMAPHORE; AUTOMATIC POWER-DOWN
I/O type	COMMON
JESD-30 code	S-PQCC-N68
JESD-609 code	e3
length	24.2062 mm
memory density	65536 bit
Memory IC Type	DUAL-PORT SRAM
memory width	8
Humidity sensitivity level	1
Number of functions	1
Number of ports	2
Number of terminals	68
word count	8192 words
character code	8000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	8KX8
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	QCCN
Encapsulate equivalent code	LDCC68,1.0SQ
Package shape	SQUARE
Package form	CHIP CARRIER
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
power supply	3.3 V
Certification status	Not Qualified
Maximum seat height	4.572 mm
Maximum standby current	0.0025 A
Minimum standby current	3 V
Maximum slew rate	0.155 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Matte Tin (Sn) - annealed
Terminal form	NO LEAD
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	24.2062 mm

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HIGH-SPEED 3.3V

8K x 8 DUAL-PORT

STATIC RAM

◆

IDT70V05S/L

Features

◆

True Dual-Ported memory cells which allow simultaneous

reads of the same memory location

High-speed access

– Commercial: 15/20/25/35/55ns (max.)

– Industrial: 20ns (max.)

Low-power operation

– IDT70V05S

Active: 400mW (typ.)

Standby: 3.3mW (typ.)

– IDT70V05L

Active: 380mW (typ.)

Standby: 660

W (typ.)

IDT70V05 easily expands data bus width to 16 bits or more

using the Master/Slave select when cascading more than

◆

one device

M/S = V

for

BUSY

output flag on Master

M/S = V

for

BUSY

input on Slave

Interrupt Flag

On-chip port arbitration logic

Full on-chip hardware support of semaphore signaling

between ports

Fully asynchronous operation from either port

TTL-compatible, single 3.3V (±0.3V) power supply

Available in 68-pin PGA and PLCC, and a 64-pin TQFP

Industrial temperature range (-40°C to +85°C) is available

for selected speeds

Green parts available, see ordering information

Functional Block Diagram

R/W

I/O

- I/O

I/O

Control

BUSY

(1,2)

I/O

Control

I/O

-I/O

BUSY

12R

(1,2)

12L

Address

Decoder

MEMORY

ARRAY

Address

Decoder

R/W

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

R/W

SEM

(2)

INT

NOTES:

1. (MASTER):

BUSY

is output; (SLAVE):

BUSY

is input.

BUSY

outputs and

INT

outputs are non-tri-stated push-pull.

M/S

SEM

INT

(2)

2942 drw 01

JUNE 2012

DSC 2941/10

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