IDT71V65803150BQGI datasheet, PDF

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IDT71V65803150BQGI: DescriptionZBT SRAM, 512KX18, 3.8ns, CMOS, PBGA165, 13.0 X 15.0 MM, ROHS COMPLIANT, FBGA-165; Categorystorage storage; File Size5MB，26 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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IDT71V65803150BQGI Overview

ZBT SRAM, 512KX18, 3.8ns, CMOS, PBGA165, 13.0 X 15.0 MM, ROHS COMPLIANT, FBGA-165

IDT71V65803150BQGI Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
Parts packaging code	BGA
package instruction	TBGA,
Contacts	165
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Maximum access time	3.8 ns
Other features	PIPELINED ARCHITECTURE
JESD-30 code	R-PBGA-B165
JESD-609 code	e1
length	15 mm
memory density	9437184 bit
Memory IC Type	ZBT SRAM
memory width	18
Humidity sensitivity level	3
Number of functions	1
Number of terminals	165
word count	524288 words
character code	512000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	512KX18
Package body material	PLASTIC/EPOXY
encapsulated code	TBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum supply voltage (Vsup)	3.465 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	TIN SILVER COPPER
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
width	13 mm

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256K x 36, 512K x 18

3.3V Synchronous ZBT™ SRAMs

ZBT™ Feature

3.3V I/O, Burst Counter

Pipelined Outputs

◆

IDT71V65603/Z

IDT71V65803/Z

Features

The IDT71V65603/5803 are 3.3V high-speed 9,437,184-bit

(9 Megabit) synchronous SRAMS. They are designed to eliminate dead bus

cycles when turning the bus around between reads and writes, or writes and

reads. Thus, they have been given the name ZBT

, or Zero Bus Turnaround.

Description

256K x 36, 512K x 18 memory configurations

Supports high performance system speed - 150MHz

(3.8ns Clock-to-Data Access)

ZBT

Feature - No dead cycles between write and read cycles

Internally synchronized output buffer enable eliminates the

need to control

Single R/W (READ/WRITE) control pin

Positive clock-edge triggered address, data, and control

signal registers for fully pipelined applications

4-word burst capability (interleaved or linear)

Individual byte write (BW

) control (May tie active)

Three chip enables for simple depth expansion

3.3V power supply (±5%)

3.3V I/O Supply (V

DDQ

)

Power down controlled by ZZ input

Packaged in a JEDEC standard 100-pin plastic thin quad

flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch

ball grid array(fBGA).

Address and control signals are applied to the SRAM during one clock

cycle, and two cycles later the associated data cycle occurs, be it read or write.

The IDT71V65603/5803 contain data I/O, address and control signal

registers. Output enable is the only asynchronous signal and can be used

to disable the outputs at any given time.

A Clock Enable (CEN) pin allows operation of the IDT71V65603/5803 to

be suspended as long as necessary. All synchronous inputs are ignored when

(CEN) is high and the internal device registers will hold their previous values.

There are three chip enable pins (CE1, CE2,

CE2)

that allow the user

to deselect the device when desired. If any one of these three are not asserted

when ADV/LD is low, no new memory operation can be initiated. However,

any pending data transfers (reads or writes) will be completed. The data bus

will tri-state two cycles after chip is deselected or a write is initiated.

The IDT71V65603/5803 have an on-chip burst counter. In the burst

mode, the IDT71V65603/5803 can provide four cycles of data for a single

address presented to the SRAM. The order of the burst sequence is

defined by the

LBO

input pin. The

LBO

pin selects between linear and

interleaved burst sequence. The ADV/LD signal is used to load a new

external address (ADV/LD = LOW) or increment the internal burst counter

(ADV/LD = HIGH).

The IDT71V65603/5803 SRAM utilize IDT's latest high-performance

CMOS process, and are packaged in a JEDEC Standard 14mm x 20mm 100-

pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array (BGA) and

165 fine pitch ball grid array (fBGA) .

Pin Description Summary

-A

, CE

R/W

CEN

CLK

ADV/LD

LBO

I/O

-I/O

, I/O

-I/O

, V

DDQ

Address Inputs

Chip Enables

Output Enable

Read/Write Signal

Clock Enable

Individual Byte Write Selects

Clock

Advance burst address / Load new address

Linear / Interleaved Burst Order

Sleep Mode

Data Input / Output

Core Power, I/O Power

Ground

Input

I/O

Supply

Synchronous

Asynchronous

Synchronous

N/A

Synchronous

Static

Asynchronous

Synchronous

Static

5304 tbl 01

ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc.

OCTOBER 2008

DSC-5304/07

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