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IDT7007S20G

Description
Dual-Port SRAM, 32KX8, 20ns, CMOS, CPGA68, 1.800 X 1.800 INCH, 0.160 INCH HEIGHT, PGA-68
Categorystorage    storage   
File Size254KB,20 Pages
ManufacturerIDT (Integrated Device Technology)
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IDT7007S20G Overview

Dual-Port SRAM, 32KX8, 20ns, CMOS, CPGA68, 1.800 X 1.800 INCH, 0.160 INCH HEIGHT, PGA-68

IDT7007S20G Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerIDT (Integrated Device Technology)
Parts packaging codePGA
package instructionPGA-68
Contacts68
Reach Compliance Codenot_compliant
ECCN codeEAR99
Maximum access time20 ns
Other featuresINTERRUPT FLAG; SEMAPHORE; AUTOMATIC POWER-DOWN
I/O typeCOMMON
JESD-30 codeS-CPGA-P68
JESD-609 codee0
length29.464 mm
memory density262144 bit
Memory IC TypeDUAL-PORT SRAM
memory width8
Number of functions1
Number of ports2
Number of terminals68
word count32768 words
character code32000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize32KX8
Output characteristics3-STATE
ExportableYES
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codePGA
Encapsulate equivalent codePGA68,11X11
Package shapeSQUARE
Package formGRID ARRAY
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)225
power supply5 V
Certification statusNot Qualified
Maximum seat height5.207 mm
Maximum standby current0.015 A
Minimum standby current4.5 V
Maximum slew rate0.315 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formPIN/PEG
Terminal pitch2.54 mm
Terminal locationPERPENDICULAR
Maximum time at peak reflow temperature30
width29.464 mm
HIGH-SPEED
32K x 8 DUAL-PORT
STATIC RAM
Integrated Device Technology, Inc.
IDT7007S/L
FEATURES:
• True Dual-Ported memory cells which allow simulta-
neous access of the same memory location
• High-speed access
— Military: 25/35/55ns (max.)
— Commercial: 20/25/35/55ns (max.)
• Low-power operation
— IDT7007S
Active: 750mW (typ.)
Standby: 5mW (typ.)
— IDT7007L
Active: 750mW (typ.)
Standby: 1mW (typ.)
• IDT7007 easily expands data bus width to 16 bits or
more using the Master/Slave select when cascading
more than one device
M/
S
= H for
BUSY
output flag on Master,
M/
S
= L for
BUSY
input on Slave
Busy and Interrupt Flags
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
Devices are capable of withstanding greater than 2001V
electrostatic discharge
TTL-compatible, single 5V (±10%) power supply
Available in 68-pin PGA, 68-pin PLCC, and a 80-pin
TQFP
Industrial temperature range (–40°C to +85°C) is avail-
able, tested to military electrical specifications
FUNCTIONAL BLOCK DIAGRAM
OE
L
R/
OE
R
CE
L
W
L
CE
R
R/
W
R
I/O
0L
- I/O
7L
I/O
Control
I/O
Control
I/O
0R
-I/O
7R
BUSY
L(1,2)
A
14L
A
0L
Address
Decoder
15
BUSY
R
MEMORY
ARRAY
Address
Decoder
A
14R
A
0R
(1,2)
15
OE
L
R/
CE
L
W
L
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
R
R/
OE
R
W
R
SEM
R
(2)
SEM
L
(2)
INT
L
NOTES:
1. (MASTER):
BUSY
is output; (SLAVE):
BUSY
is input.
2.
BUSY
and
INT
outputs are non-tri-stated push-pull.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
M/
S
INT
R
2940 drw 01
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1996 Integrated Device Technology, Inc.
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.
OCTOBER 1996
DSC-2940/4
6.08
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