The UT54ALVC2525 is a low-voltage, minimum skew, one-
to-eight clock driver. The UT54ALVC2525 distributes a single
clock to eight, high-drive, outputs with low skew across all
outputs during both the t
PLH
and t
PHL
transitions making it
ideal for signal generation and clock distribution. The output
pins act as a single entity and will follow the state of the CLK
pin.
O
0
O
2
NC
GND
V
CC
O
4
O
6
1
2
3
4
5
6
7
14
13
12
11
10
9
8
O
1
O
3
CLK
V
CC
GND
O
5
O
7
PIN DESCRIPTION
Flatpack
Pin No.
12
3
1, 2, 6, 7, 8, 9,
13, 14
5, 11
4, 10
Name
CLK
N/C
O
n
V
DD
V
SS
I/O
I
--
O
PWR
PWR
Type
LVTTL
--
LVTTL
Power
Power
Description
Primary reference clock input. This pin must be driven by an LVTTL or
LVCMOS clock source.
No connect.
Eight output clocks.
Power supply for internal circuitry and output buffers.
Ground
RADIATION HARDNESS
The UT54ALVC2525 incorporates special design, layout, and
process features which allows operation in a limited radiation
environment.
Parameter
Total Ionizing Dose (TID)
Single Event Latchup (SEL)
1, 2
Onset Single Event Upset (SEU) LET
Threshold
3, 4
Limit
>1E6
>109
>109
1.0E14
TBD
TBD
Units
rads(Si)
MeV-cm
2
/mg
MeV-cm
2
/mg
n/cm
2
rads(Si)/sec
rads(Si)/sec
Neutron Fluence
Dose Rate Upset
Dose Rate Survivability
IN
D
EV
EL
2
Notes:
1. The UT54ALVC2525 is latchup immune to particle LETs >109 MeV-cm
2
/mg.
2. SEL temperature and voltage conditions of T
C
= +125
o
C, V
DD
= 3.6V.
3. SEU worst case temperature and voltage conditions of T
C
= +25
o
C, V
DD
=
3.0V.
4. For the UT54ALVC2525 SET performance at select operating frequency
data ranges, please contact the factory.
O
PM
EN
T
ABSOLUTE MAXIMUM RATINGS:
1
(Referenced to V
SS
)
Symbol
V
DD
V
IN
V
OUT
I
I
P
D
T
STG
T
J
Θ
JC
ESD
HBM
Description
Core Power Supply Voltage
Voltage Any Clock Input
Voltage Any Clock Output
DC Input Current
Maximum Power Dissipation
Storage Temperature
Maximum Junction Temperature
2
Thermal Resistance, Junction to Case
ESD Protection (Human Body Model) - Class II
Limits
-0.3 to 4.0
-0.3 to V
DD
+ 0.3
-0.3 to V
DD
+ 0.3
+10
TBD
-65 to +150
+150
20
>3000
Units
V
V
V
mA
W
°C
°C
°C/W
V
RECOMMENDED OPERATING CONDITIONS:
Symbol
V
DD
V
IN
V
OUT
T
C
Core Operating Voltage
Voltage Clock Input
Voltage Any Clock Output
PM
Description
EN
T
Notes:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device
at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability and performance.
2. Maximum junction temperature may be increased to +175°C during burn-in and steady-static life.
Limits
2.0 to 3.6
0 to V
DD
0 to V
DD
Units
V
V
V
°C
IN
D
EV
EL
3
Case Operating Temperature
O
-55 to +125
DC OUTPUT ELECTRICAL CHARACTERISTICS (Pre- and Post-Radiation)*
(V
DD
= 2.0V to 3.6V; T
C
= -55°C to +125°C)
Symbol
Description
Conditions
V
DD
2.0V
2.75V
3.0V
3.6V
2.0V
2.75V
3.0V
3.6V
I
OL
= 12mA
I
OL
= 12mA
I
OL
= 12mA
I
OL
= 12mA
I
OH
= -12mA
I
OH
= -12mA
I
OH
= -12mA
I
OH
= -12mA
V
OUT
= V
DD
and V
SS
V
IN
= V
DD
or V
SS
2.0V
2.75V
3.0V
3.6V
2.0V
2.75V
3.0V
3.6V
2.0V
3.6V
3.6V
1.6
2.2
2.4
3.0
Min.
1.25
1.5
1.75
2.0
Max.
Units
V
IH1
High level input voltage
V
V
IL1
Low level input voltage
0.7
0.8
0.8
0.8
0.4
0.4
0.4
0.4
V
V
OL
Low level output voltage
V
V
OH
High level output voltage
V
T
-1
I
OS2
I
IL
Short-circuit output current
Input leakage current
-300
-600
300
600
1
mA
µΑ
I
DDQ
Quiescent Supply Current
Pre-Rad 25
o
C
Pre-Rad -55
o
C to +125
o
C
Post-Rad 25
o
C
Pre-Rad 25
o
C
Pre-Rad -55
o
C to +125
o
C
Post-Rad 25
o
C
V
IN
= V
DD
or V
SS
EN
PM
2.0V
2.0
mA
mA
mA
mA
mA
mA
1
2
mW/MHz
mW/MHz
mW/MHz
mW/MHz
mW/MHz
mW/MHz
TBD
TBD
3.6V
4.0
TBD
TBD
2.0V
2.75V
3.0V
3.6V
0V
0V
P
TOTAL
Total power dissipation
EV
C
L
= 50pF
EL
O
IN
C
IN4
C
OUT4
D
2.5
3.75
15
15
mW/MHz
Input capacitance
f = 1MHz
f = 1MHz
pF
pF
Output capacitance
Notes:
* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019, Condition A up to a TID level of 1.0E6 rad(Si).
1. Functional tests are conducted in accordance with MIL-STD-883 with the following test conditions: V
IH
=V
IH
(min) +20%, -0% V
IL
=V
IL
(max)+0%, -50%, as
specified herein for the LVTTL and LVCMOS inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to
V
IH
(min), V
IL
(max).
2. Supplied as a design limit. Neither guaranteed nor tested.
3. When measuring the dynamic supply current, all outputs are loaded in accordance with the equivalent test load defined in figure 3.
4. Capacitance is measured for initial qualification and when design changes may affect the input/output capacitance. Capacitance is measured between the designated
terminal and the VSS at a frequency of 1MHz and a signal amplitude of 50mV rms maximum.
4
AC OUTPUT ELECTRICAL CHARACTERISTICS (Pre- and Post-Radiation)*
(V
DD
= 2.0V to 3.6V; T
C
= -55°C to +125°C)
(Note 1, 2)
DUT
Description
Input rise/fall time
Propagation delay:
CLK to On,
high-to-low transition
Propagation delay:
CLK to On,
low-to-high transition
Maximum skew:
common edge,
output-to-output,
low-to-high transition
Maximum skew:
common edge,
output-to-output,
CLK
high-to-low transition
Output rise/fall time
V
Qn
V
DD
DD
Condition
V
IH
(min) - V
IL
(max)
Measured as transition time between
V
IN
= V
DD
÷2
to V
OUT
= V
DD
÷2
V
DD
C
L
3.6V
2.0V
2.75V
3.0V
3.6V
2.0V
2.75V
3.0V
3.6V
2.0V
2.75V
3.0V
3.6V
2.0V
2.75V
3.0V
3.6V
V
DD
/2
Min.
Max.
20
Unit
ns/V
150Ω
100Ω
3.5
3.0
DUT
2.75
2.25
3.25
2.75
2.5
2.0
7.5
5.5
5.25
4.75
7.25
5.25
5.0
4.5
ns
Measured as
Figure 3.
time between
transition
V
IN
=
Load
to V
OUT
Dynamic
Output Test
V
DD
÷2
Circuit
= V
DD
÷2
Power
100Ω
ns
150Ω
C
L
Supply Current Measurements
0.7
Figure 4.
0.55
Clock Output AC Test Load Circuit
ns
0.55
Note: This is not the recommended termination
0.5
for normal user operation.
O
0
Part-part skew
O
7
Propagation delay balance:
difference between same output,
low-to-high and
high-to-low transitions
Maximum skew:
opposite edge,
output-to-output variation
Measured as transition time between
to V
OUT
= V
DD
÷2
V
IN
= V
DD
÷2
t
PHL
O
5
t
OSHL
Measured as transition time between
V
IN
= V
DD
÷2
to V
OUT
= V
DD
÷2
2.0V
2.75V
t
PLH
3.0V
3.6V
t
2.0V
2.75V
3.0V
3.6V
PM
OSLH
Skew between the outputs of any two devices under
identical settings and conditions
(V
DD
, temp, air flow, frequency, etc).
V
DD
/2
2.0V
3.6V
EN
0.75
0.50
Measured as transition time between
20% * V
DD
and 80% * V
DD
2.0V
3.6V
1.0
0.75
2.0
1.5
V
DD
/2
0.75
0.5
0.35
0.3
0.5
0.25
0.18
0.1
ns
EL
Figure 5. AC Timing Diagram
IN
D
Notes:
* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019, Condition A up to a TID level of 1.0E6 rad(Si).
1. Test load = 40pF, terminated to V
DD
÷
2. All outputs are equally loaded. Reference figure 4 for clock output loading that is equivalent to the load circuit used for all
AC testing.
2. Reference Figures 5 and 6 for AC timing diagrams.
3. Supplied only as a design guideline, neither tested nor guaranteed.
4. Guaranteed by characterization, but not tested.
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