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BU-61840B3-800S

Description
Mil-Std-1553 Controller, 2 Channel(s), 0.125MBps, CMOS, PBGA128, 0.815 X 0.815 INCH, 0.140 INCH HEIGHT, BGA-128
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size764KB,60 Pages
ManufacturerData Device Corporation
Download Datasheet Parametric View All

BU-61840B3-800S Overview

Mil-Std-1553 Controller, 2 Channel(s), 0.125MBps, CMOS, PBGA128, 0.815 X 0.815 INCH, 0.140 INCH HEIGHT, BGA-128

BU-61840B3-800S Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerData Device Corporation
Parts packaging codeBGA
package instructionBGA,
Contacts128
Reach Compliance Codecompliant
Address bus width16
boundary scanNO
maximum clock frequency20 MHz
letter of agreementMIL-STD-1553A; MIL-STD-1553B; MIL-STD-1760; MCAIR; STANAG-3838
Data encoding/decoding methodsBIPH-LEVEL(MANCHESTER)
Maximum data transfer rate0.125 MBps
External data bus width16
JESD-30 codeS-PBGA-B128
JESD-609 codee0
low power modeNO
Number of serial I/Os2
Number of terminals128
Maximum operating temperature70 °C
Minimum operating temperature
Package body materialPLASTIC/EPOXY
encapsulated codeBGA
Package shapeSQUARE
Package formGRID ARRAY
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Certification statusNot Qualified
Maximum seat height3.58 mm
Maximum supply voltage3.6 V
Minimum supply voltage3 V
Nominal supply voltage3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTIN LEAD
Terminal formBALL
Terminal pitch1 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperatureNOT SPECIFIED
uPs/uCs/peripheral integrated circuit typeSERIAL IO/COMMUNICATION CONTROLLER, MIL-STD-1553
BU-6174X/6184X/6186X
Make sure the next
Card you purchase
has...
TM
ENHANCED MINIATURE ADVANCED
COMMUNICATIONS ENGINE
FEATURES
Fully Integrated 1553A/B Notice 2,
McAir, STANAG 3838 Interface Terminal
Compatible with Mini-ACE (Plus)
and ACE Generations
Choice of :
-
RT or BC/RT/MT In Same Footprint
- RT or BC/RT/MT with 4K RAM
- BC/RT/MT with 64K RAM, and RAM
parity
Choice of 5V or 3.3V Logic
• Package Options:
- 1" Square Ceramic Flat Pack or
Gull Wing
- 0.815" Square BGA
DESCRIPTION
The Enhanced Miniature Advanced Communications Engine
(Enhanced Mini-ACE) family of MIL-STD-1553 terminals provide
complete interfaces between a host processor and a 1553 bus, and
integrate dual transceiver, protocol logic, and 4K words or 64K words
of RAM.
These terminals are nearly 100% footprint and software compatible
with the previous generation Mini-ACE (Plus) terminals, and are soft-
ware compatible with the older ACE series.
At 0.815" square, the Enhanced Mini-ACE BGA package option pro-
vides the smallest footprint in the industry.
They are powered by a choice of 5V or 3.3V logic. Multiprotocol sup-
port of MIL-STD-1553A/B and STANAG 3838, including versions
incorporating McAir compatible transmitters, is provided. There is a
choice of 10, 12, 16, or 20 MHz clocks. The BC/RT/MT versions with
64K words of RAM include built-in RAM parity checking.
BC features include a built-in message sequence control engine, with
a set of 20 instructions. This provides an autonomous means of
implementing multi-frame message scheduling, message retry
schemes, data double buffering, asynchronous message insertion,
and reporting to the host CPU. The Enhanced Mini-ACE incorporates
a fully autonomous built-in self-test, which provides comprehensive
testing of the internal protocol logic and/or RAM.
The RT offers the same choices of subaddress buffering as the ACE
and Mini-ACE (Plus), along with a global circular buffering option,
50% rollover interrupt for circular buffers, an interrupt status queue,
and an "Auto-boot" option to support MIL-STD-1760.
These terminals provide the same flexibility in host interface configu-
rations as the ACE/Mini-ACE, along with a reduction in the host
processor's worst case holdoff time.
Data Device Corporation
105 Wilbur Place
Bohemia, New York 11716
631-567-5600 Fax: 631-567-7358
www.ddc-web.com
5V Transceiver with 1760 and McAir
Compatible Options
Comprehensive Built-In Self-Test
Flexible Processor/Memory Interface,
with Reduced Host Wait Time
Choice of 10, 12, 16, or 20 MHz Clock
Highly Autonomous BC with
Built-In Message Sequence Control:
- Frame Scheduling
- Branching
- Asynchronous Message Insertion
- General Purpose Queue
- User-defined Interrupts
Advanced RT Functions
- Global Circular Buffering
- Interrupt Status Queue
- 50% Circular Buffer Rollover
Interrupts
Selective Message Monitor
- Selection by Address, T/R Bit,
Subaddress
- Command and Data Stacks
- 50% and 100% Stack Rollover
Interrupts
FOR MORE INFORMATION CONTACT:
Technical Support:
1-800-DDC-5757 ext. 7234
©
2000 Data Device Corporation
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