EEWORLDEEWORLDEEWORLD

Part Number

Search

531MB372M000DGR

Description
LVPECL Output Clock Oscillator, 372MHz Nom, ROHS COMPLIANT, SMD, 6 PIN
CategoryPassive components    oscillator   
File Size215KB,12 Pages
ManufacturerSilicon Laboratories Inc
Environmental Compliance  
Download Datasheet Parametric View All

531MB372M000DGR Overview

LVPECL Output Clock Oscillator, 372MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

531MB372M000DGR Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerSilicon Laboratories Inc
package instructionROHS COMPLIANT, SMD, 6 PIN
Reach Compliance Codeunknown
Other featuresTAPE AND REEL
maximum descent time0.35 ns
Frequency Adjustment - MechanicalNO
frequency stability20%
JESD-609 codee4
Manufacturer's serial number531
Installation featuresSURFACE MOUNT
Nominal operating frequency372 MHz
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Oscillator typeLVPECL
physical size7.0mm x 5.0mm x 1.85mm
longest rise time0.35 ns
Maximum supply voltage3.63 V
Minimum supply voltage2.97 V
Nominal supply voltage3.3 V
surface mountYES
maximum symmetry55/45 %
Terminal surfaceNickel/Gold (Ni/Au)
S i 5 3 0 / 5 31
R
EVISION
D
C
R Y S TA L
O
S C I L L A T O R
(XO)
(10 M H
Z T O
1.4 G H
Z
)
Features
Available with any-rate output
frequencies from 10 MHz to 945 MHz
and select frequencies to 1.4 GHz
3rd generation DSPLL
®
with superior
jitter performance
3x better frequency stability than
SAW-based oscillators
Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
Si5602
Ordering Information:
See page 7.
Applications
SONET/SDH
Networking
SD/HD video
Test and measurement
Clock and data recovery
FPGA/ASIC clock generation
Pin Assignments:
See page 6.
(Top View)
NC
OE
GND
1
2
3
6
5
4
V
DD
Description
The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry
to provide a low jitter clock at high frequencies. The Si530/531 is available
with any-rate output frequency from 10 to 945 MHz and select frequencies to
1400 MHz. Unlike a traditional XO, where a different crystal is required for
each output frequency, the Si530/531 uses one fixed crystal to provide a
wide range of output frequencies. This IC based approach allows the crystal
resonator to provide exceptional frequency stability and reliability. In addition,
DSPLL clock synthesis provides superior supply noise rejection, simplifying
the task of generating low jitter clocks in noisy environments typically found in
communication systems. The Si530/531 IC based XO is factory configurable
for a wide variety of user specifications including frequency, supply voltage,
output format, and temperature stability. Specific configurations are factory
programmed at time of shipment, thereby eliminating long lead times
associated with custom oscillators.
®
CLK–
CLK+
Si530 (LVDS/LVPECL/CML)
OE
NC
GND
1
2
3
6
5
4
V
DD
Functional Block Diagram
V
DD
CLK– CLK+
NC
CLK
Si530 (CMOS)
Fixed
Frequency
XO
Any-rate
10–1400 MHz
DSPLL
®
Clock
Synthesis
OE
NC
GND
1
2
3
6
5
4
V
DD
CLK–
CLK+
Si531 (LVDS/LVPECL/CML)
OE
GND
Rev. 1.1 6/07
Copyright © 2007 by Silicon Laboratories
Si530/531
LPC54102 running ADC routine
[i=s]This post was last edited by littleshrimp on 2015-4-7 09:17[/i]...
littleshrimp NXP MCU
EEWORLD University - LabVIEW 2010 from entry to mastery
LABVIEW2010 from entry to mastery : https://training.eeworld.com.cn/course/4341"LabVIEW 2010 Chinese Edition Virtual Instruments from Beginner to Master" explains the application technology and applic...
老白菜 Embedded System
Where is the best place to place the ESD on the PCB?
Where is the best place to place the ESD on the PCB?...
luck_gfb Analogue and Mixed Signal
TO USB driver development routine problem
I use Cy7c68013A for development. Other routines have been completed, and the control transmission and data search have been completed. Only DriverObject->MajorFunction[IRP_MJ_WRITE] = Ezusb_Write; //...
daviu1234 Embedded System
EEWORLD University ---- MSP432?: The perfect combination of low-power DNA and ARM_2016 TI Embedded Products Seminar Record
MSP432?: The perfect combination of low-power DNA and ARM_2016 TI Embedded Products Seminar Record : https://training.eeworld.com.cn/course/3738This course is a record of the 2016 TI Embedded Products...
soso MCU
Telecommunications Technology Glossary: EDGE Technology Explained
EDGE is the abbreviation of Enhanced Data Rate for GSM Evolution. EDGE is a transitional technology from GSM to 3G. It mainly adopts a new modulation method in the GSM system, namely the most advanced...
maker RF/Wirelessly

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 1940  790  2696  534  2381  40  16  55  11  48 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号