GS8662S09GE-167IT datasheet, PDF

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GS8662S09GE-167IT: DescriptionDDR SRAM, 8MX9, 0.5ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, MO-216CAB-1, FPBGA-165; Categorystorage storage; File Size1MB，35 Pages; ManufacturerGSI Technology; Websitehttp://www.gsitechnology.com/; Environmental Compliance

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GS8662S09GE-167IT Overview

DDR SRAM, 8MX9, 0.5ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, MO-216CAB-1, FPBGA-165

GS8662S09GE-167IT Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	GSI Technology
Parts packaging code	BGA
package instruction	LBGA,
Contacts	165
Reach Compliance Code	unknown
ECCN code	3A991.B.2.B
Maximum access time	0.5 ns
Other features	PIPELINED ARCHITECTURE
JESD-30 code	R-PBGA-B165
JESD-609 code	e1
length	17 mm
memory density	75497472 bit
Memory IC Type	DDR SRAM
memory width	9
Humidity sensitivity level	3
Number of functions	1
Number of terminals	165
word count	8388608 words
character code	8000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	8MX9
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Maximum seat height	1.5 mm
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	TIN SILVER COPPER
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	15 mm

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GS8662S08/09/18/36E-250/200/167

165-Bump BGA

Commercial Temp

Industrial Temp

Features

• Simultaneous Read and Write SigmaSIO™ DDR-II Interface

• JEDEC-standard pinout and package

• Dual Double Data Rate interface

• Byte Write controls sampled at data-in time

• DLL circuitry for wide output data valid window and future

frequency scaling

• Burst of 2 Read and Write

• 1.8 V +100/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

• Pipelined read operation

• Fully coherent read and write pipelines

• ZQ mode pin for programmable output drive strength

• IEEE 1149.1 JTAG-compliant Boundary Scan

• Pin-compatible with future 144Mb devices

• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package

• RoHS-compliant 165-bump BGA package available

72Mb Burst of 2

SigmaSIO™ DDR-II SRAM

250 MHz–167 MHz

1.8 V V

1.8 V and 1.5 V I/O

for

GS8662S08/09/18/36 are built in compliance with the

SigmaSIO DDR-II SRAM pinout standard for Separate I/O

synchronous SRAMs. They are 75,497,472-bit (72Mb)

SRAMs. These are the first in a family of wide, very low

voltage HSTL I/O SRAMs designed to operate at the speeds

needed to implement economical high performance

networking systems.

Parameter Synopsis

-250

4.0 ns

-200

5.0 ns

0.45 ns

-167

6.0 ns

0.5 ns

tKHKH

tKHQV

0.45 ns

Rev: 1.07 8/2012

1/35

sig

SigmaSIO™ DDR-II Family Overview

n—

sco

inu

Clocking and Addressing Schemes

A Burst of 2 SigmaSIO DDR-II SRAM is a synchronous

device. It employs dual input register clock inputs, K and K.

The device also allows the user to manipulate the output

K clocks are routed internally to fire the output registers

instead. Each Burst of 2 SigmaSIO DDR-II SRAM also

supplies Echo Clock outputs, CQ and CQ, which are

synchronized with read data output. When used in a source

synchronous clocking scheme, the Echo Clock outputs can be

used to fire input registers at the data’s destination.

Each internal read and write operation in a SigmaSIO DDR-II

B2 RAM is two times wider than the device I/O bus. An input

data bus de-multiplexer is used to accumulate incoming data

before it is simultaneously written to the memory array. An

output data multiplexer is used to capture the data produced

from a single memory array read and then route it to the

appropriate output drivers as needed. Therefore, the address

field of a SigmaSIO DDR-II B2 is always one address pin less

than the advertised index depth (e.g., the 8M x 8 has a 4M

addressable index).

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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