DS2009
DS2009
512 x 9 FIFO Chip
FEATURES
PIN ASSIGNMENT
W
D8
D3
D2
D1
D0
XI
FF
Q0
Q1
Q2
Q3
Q8
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
D4
D5
D6
D7
D2
D1
D0
D3
D8
W
NC
VCC
D4
D5
4 3 2 1 32 31 30
5
29
6
28
7
27
8
26
9
25
10
24
11
23
12
22
13 15
17 19 21
14 16
18
20
Q3
Q8
GND
NC
R
Q4
Q5
32-Pin PLCC
051994 1/14
D6
D7
NC
FL/RT
RS
EF
X0/HF
Q7
Q6
•
First-in, first-out memory-based architecture
•
Flexible 512 x 9 organization
•
Low-power HCMOS technology
•
Asynchronous and simultaneous read/write
•
Bidirectional applications
•
Fully expandable by word width or depth
•
Empty and full warning flags
•
Half-full flag capability in single-device mode
•
Retransmit capability
•
High performance
•
Available in 35 ns, 50 ns, 65 ns, 80 ns, and 120 ns
access times
FL/RT
XI
RS
FF
EF
Q0
X0/HF
Q1
Q7
NC
Q6
Q2
Q5
Q4
R
28-Pin DIP(300 and 600 Mil)
PIN DESCRIPTION
W
R
RS
FL/RT
D
0-8
Q
0-8
XI
XO/HF
FF
EF
V
CC
GND
NC
–
–
–
–
–
–
–
–
–
–
–
–
–
WRITE
READ
RESET
First Load/Retransmit
Data In
Data Out
Expansion In
Expansion Out/Half Full
Full Flag
Empty Flag
5 Volts
Ground
No Connect
•
Optional industrial temperature range -40°C to +85°C
available, designated N
DESCRIPTION
The DS2009 512 x 9 FIFO Chip implements a first-in,
first-out algorithm featuring asynchronous read/write
operations, full, empty and half-full flags, and unlimited
expansion capability in both word size and depth. The
main application of the DS2009 is as a rate buffer, sourc-
ing and absorbing data at different rates (e.g., interfac-
ing fast processors and slow peripherals). The full and
empty flags are provided to prevent data overflow and
underflow. A half-full flag is available in the single-de-
vice and width-expansion configurations. The data is
loaded and emptied on a first-in, first-out (FIFO) basis,
and the latency for the retrieval of data is approximately
one load cycle (write). Since the writes and reads are
internally sequential, thereby requiring no address infor-
mation, the pinout definition will serve this and future
higher-density devices. The ninth bit is provided to sup-
port control or parity functions.
ECopyright
1995 by Dallas Semiconductor Corporation.
All Rights Reserved. For important information regarding
patents and other intellectual property rights, please refer to
Dallas Semiconductor databooks.
DS2009
OPERATION
Unlike conventional shift register-based FIFOs, the
DS2009 employs a memory-based architecture where-
in a byte written into the device does not ripple through.
Instead, a byte written into the DS2009 is stored at a
specific location where it remains until over-written. The
byte can be read and re-read as often as desired.
Twin address pointers (ring counters) automatically
generate the address required for each write and read
operation. The empty/full flag circuit prevents illogical
operations, such as reading unwritten bytes (reading
while empty) or over-writing unread bytes (writing while
full). Once a byte stored at a given address has been
read, it can be over-written.
Address pointers automatically loop back to address
zero after reaching address 511. The empty/full status
of the FIFO is therefore a function of the distance be-
tween the pointers, not of their absolute location. As
long as the pointers do not catch one another, the FIFO
can be written and read continuously without ever be-
coming full or empty.
Resetting the FIFO simply resets the address pointers
to address zero. Pulsing retransmit resets the read ad-
dress pointer without affecting the write address pointer.
With conventional FIFOs, implementation of a larger
FIFO is accomplished by cascading the individual FI-
FOs. The penalty of cascading is often unacceptable
ripple-through delays. The DS2009 allows implementa-
tion of very large FIFOs with no timing penalties. The
memory-based architecture of the DS2009 can connect
the read, write, data in, and data out lines of the DS2009
in parallel. The write and read control circuits of the indi-
vidual FIFOs are then automatically enabled and dis-
abled through the expansion in and expansion out pins
as appropriate (see the ‘‘Expansion Timing” section for
a more complete discussion).
BLOCK DIAGRAM
Figure 1
9
D
0
-D
8
9
Q
0
-Q
8
INPUT
BUFFER
W
WRITE
CONTROL
WRITE
ADDRESS
POINTER
OUTPUT
BUFFER
READ
ADDRESS
POINTER
READ
CONTROL
R
512 X 9
MEMORY ARRAY
FF
FLAG
LOGIC
EF
XI
EXPANSION LOGIC
XO/HF
RS
RESET/RETRANSMIT
LOGIC
FL/RT
051994 2/14
DS2009
SINGLE DEVICE CONFIGURATION
A single DS2009 can be used when application require-
ments are for 512 words or less. The DS2009 is placed in
single device configuration mode when the chip is reset
with the Expansion In pin (XI) grounded (see Figure 2).
A SINGLE 512 X 9 FIFO CONFIGURATION
Figure 2
(EF) EMPTY FLAG
WRITE (W)
(R) READ
9
9
DATA IN (Q0-Q8)
DS2009
DATA IN (D0-D8)
FULL FLAG (FF)
(EF) EMPTY FLAG
RESET (RS)
(RT) RETRANSMIT
EXPANSION IN (XI)
A 512 X 18 FIFO CONFIGURATION (WIDTH EXPANSION)
Figure 3
18
DATA IN
9
XO/HF
9
(XO/HF) EXPANSION
OUT/HALF-FULL
WRITE (W)
(R) READ
FULL FLAG (FF)
DS2009
(RT) RETRANSMIT
RESET (RS)
9
9
DS2009
(EF) EMPTY FLAG
18
EXPANSION IN (XI)
(XI)
DATA OUT
NOTE:
Flag detection is accomplished by monitoring the FF, EF and HF signals on either (any) device used in the width ex-
pansion configuration. Do not connect flag output signals together.
051994 3/14
DS2009
DEPTH EXPANSION (DAISY CHAIN)
The DS2009 can easily be adapted to applications
where more than 512 words are required. Figure 4 dem-
onstrates depth expansion using three DS2009s. Any
depth can be attained by adding DS2009s.
External logic is needed to generate a composite full
flag and empty flag. This requires the ORing of all EFs
and the ORing of all FFs (i.e., all must be set to generate
the correct composite FF or EF).
The DS2009 operates in the depth expansion configura-
tion after the chip is reset under the following conditions.
1. The first device must be designated by grounding
the First Load pin (FL). The retransmit function is not
allowed in the depth expansion mode.
2. All other devices must have FL in the high state.
3. The Expansion Out (XO) pin of each device must be
tied to the Expansion In (XI) pin of the next device.
The half-full capability is not allowed in depth expan-
sion.
A 1536 X 9 FIFO CONFIGURATION (DEPTH EXPANSION)
Figure 4
X0
W
FF
DATA IN
(D0 - D8)
9
9
DS2009
FL
V
CC
XI
XO
FULL
EMPTY
EF
9
DATA OUT
(Q0 - Q8)
R
FF
9
DS2009
EF
FL
XI
XO
FF
9
RS
DS2009
FL
EF
XI
COMPOUND EXPANSION
The two expansion techniques described above can be
applied together in a straightforward manner to achieve
large FIFO arrays (see Figure 5).
BIDIRECTIONAL APPLICATIONS
Bidirectional applications that require data buffering be-
tween two systems (each system capable of read and
write operations) can be achieved by pairing DS2009s
as shown in Figure 6. Care must be taken to assure that
the appropriate flag is monitored by each system (i.e.,
FF is monitored on the device where W is used; EF is
monitored on the device where R is used). Both depth
expansion and width expansion can be used in this
mode.
051994 4/14
DS2009
COMPOUND FIFO EXPANSION
Figure 5
Q0–Q8
Q0–Q17
Q0–QN
Q0–Q8
R, W, RS
DS2009
DEPTH EXPANSION
BLOCK
Q9–Q17
DS2009
DEPTH EXPANSION
BLOCK
Q(N–8)–QN
DS2009
DEPTH EXPANSION
BLOCK
D0–D8
D9–D17
D(N–8)–DN
D0–DN
D9–DN
D18–DN
D(N–8)–DN
NOTES:
1. For depth expansion block diagram see ‘‘Depth Expansion” section and Figure 4.
2. For flag operation see ‘‘Width Expansion” section and Figure 3.
BIDIRECTIONAL FIFO APPLICATION
Figure 6
W
A
FF
A
DS2009
D
A
0-8
Q
B
0-8
R
B
EF
B
SYSTEM A
SYSTEM B
Q
A
0-8
R
A
EF
A
DS2009
D
B
0-8
W
B
FF
B
HALF-FULL CAPABILITY
In the single-device and width-expansion modes, the
XO/HF output acts as an indication of a half-full memory.
(XI must be tied low.) After half of the memory is filled,
and at the falling edge of the next write operation, the
Half-Full Flag (HF) will be set to low and will remain low
until the difference between the write pointer and read
pointer is less than or equal to one half of the total
memory of the device. The half-full flag is then reset
(forced high) by the rising edge of the read operation.
WRITE MODE
The DS2009 initiates a write cycle (see Figure 7) on the
falling edge of the write enable control input (W), pro-
vided that the Full Flag (FF) is not asserted. Data setup
051994 5/14
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