BLM7G1822S-80AB;
BLM7G1822S-80ABG
LDMOS 2-stage power MMIC
Rev. 2 — 1 July 2015
Product data sheet
1. Product profile
1.1 General description
The BLM7G1822S-80AB(G) is a dual section, asymmetric, 2-stage power MMIC using
NXP’s state of the art GEN7 LDMOS technology. This multiband device is perfectly suited
as small cell final stage in Doherty configuration, or as general purpose driver in the
1805 MHz to 2170 MHz frequency range. Available in gull wing or straight lead outline.
Table 1.
Performance
Typical RF performance at T
case
= 25
C. Test signal: 3GPP test model 1; 64 DPCH; PAR = 9.9 dB
at 0.01% probability on CCDF; specified in a class-AB production circuit.
Test signal
single carrier W-CDMA
carrier section
peaking section
[1]
f
(MHz)
2167.5
2167.5
I
Dq1
[1]
(mA)
40
80
I
Dq2
[1]
(mA)
120
240
V
DS
(V)
28
28
P
L(AV)
(W)
4
8
G
p
(dB)
30
28.3
D
(%)
24
24
ACPR
5M
(dBc)
39.5
36
I
Dq1
represents driver stage; I
Dq2
represents final stage.
1.2 Features and benefits
Designed for broadband operation (frequency 1805 MHz to 2170 MHz)
High section-to-section isolation enabling multiple combinations
High Doherty efficiency thanks to 2 : 1 asymmetry
Integrated temperature compensated bias
Biasing of individual stages is externally accessible
Integrated ESD protection
Excellent thermal stability
High power gain
On-chip matching for ease of use
Compliant to Directive 2002/95/EC, regarding restriction of hazardous substances
(RoHS)
1.3 Applications
RF power MMIC for W-CDMA base stations in the 1805 MHz to 2170 MHz frequency
range. Possible circuit topologies are the following as also depicted in
Section 8.1:
Asymmetric final stage in Doherty configuration
Asymmetric driver for high power Doherty amplifier
NXP Semiconductors
BLM7G1822S-80AB(G)
LDMOS 2-stage power MMIC
2. Pinning information
2.1 Pinning
Transparent top view
The exposed backside of the package is the ground terminal of the device.
Fig 1.
Pin configuration
2.2 Pin description
Table 2.
Symbol
V
DS(A1)
V
GS(A2)
V
GS(A1)
RF_IN_A
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
RF_IN_B
V
GS(B1)
V
GS(B2)
V
DS(B1)
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Description
drain-source voltage of carrier section, driver stage (A1)
gate-source voltage of carrier section, final stage (A2)
gate-source voltage of carrier section, driver stage (A1)
RF input carrier section (A)
not connected
not connected
not connected
not connected
not connected
not connected
RF input peaking section (B)
gate-source voltage of peaking section, driver stage (B1)
gate-source voltage of peaking section, final stage (B2)
drain-source voltage of peaking section, driver stage (B1)
BLM7G1822S-80AB_S-80ABG
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 2 — 1 July 2015
2 of 18
NXP Semiconductors
BLM7G1822S-80AB(G)
LDMOS 2-stage power MMIC
Table 2.
Symbol
Pin description
…continued
Pin
15
16
Description
RF output peaking section (B) / drain-source voltage of peaking section, final stage (B2)
RF output carrier section (A) / drain-source voltage of carrier section, final stage (A2)
RF_OUT_B/V
DS(B2)
RF_OUT_A/V
DS(A2)
GND
flange RF ground
3. Ordering information
Table 3.
Ordering information
Package
Name
BLM7G1822S-80AB
BLM7G1822S-80ABG
HSOP16F
HSOP16
Description
plastic, heatsink small outline package; 16 leads (flat)
plastic, heatsink small outline package; 16 leads
Version
SOT1211-2
SOT1212-2
Type number
4. Block diagram
Fig 2.
Block diagram
5. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
DS
V
GS
T
stg
T
j
T
case
[1]
Parameter
drain-source voltage
gate-source voltage
storage temperature
junction temperature
case temperature
Conditions
Min
-
0.5
65
[1]
Max
65
+13
+150
225
150
Unit
V
V
C
C
C
-
-
Continuous use at maximum temperature will affect the reliability. For details refer to the online MTF calculator.
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
BLM7G1822S-80AB_S-80ABG
Product data sheet
Rev. 2 — 1 July 2015
3 of 18
NXP Semiconductors
BLM7G1822S-80AB(G)
LDMOS 2-stage power MMIC
6. Thermal characteristics
Table 5.
Symbol
R
th(j-c)
Thermal characteristics
Parameter
thermal resistance from junction to case
Conditions
final stage; T
case
= 90
C;
P
L
= 1.26 W
driver stage; T
case
= 90
C;
P
L
= 1.26 W
Peaking section
R
th(j-c)
thermal resistance from junction to case
final stage; T
case
= 90
C;
P
L
= 2.52 W
driver stage; T
case
= 90
C;
P
L
= 2.52 W
[1]
When operated with a CW signal.
[1]
[1]
[1]
[1]
Value
2.4
7.6
1.5
5.5
Unit
K/W
K/W
K/W
K/W
Carrier section
7. Characteristics
Table 6.
DC characteristics
T
case
= 25
C; per section unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Carrier section
Final stage
V
(BR)DSS
drain-source breakdown voltage
V
GSq
I
Dq
/T
I
DSS
I
DSX
I
GSS
gate-source quiescent voltage
quiescent drain current variation with temperature
drain leakage current
drain cut-off current
gate leakage current
V
GS
= 0 V; I
D
= 0.302 mA
V
DS
= 28 V; I
D
= 120 mA
V
DS
= 28 V; I
D
= 120 mA
T
case
=
40 C
to +85
C
V
GS
= 0 V; V
DS
= 28 V
V
GS
= 5.55 V; V
DS
= 10 V
V
GS
= 1.0 V; V
DS
= 0 V
V
GS
= 0 V; I
D
= 0.058 mA
V
DS
= 28 V; I
D
= 40 mA
V
DS
= 28 V; I
D
= 40 mA
I
Dq
/T
I
DSS
I
DSX
I
GSS
quiescent drain current variation with temperature
drain leakage current
drain cut-off current
gate leakage current
T
case
=
40 C
to +85
C
V
GS
= 0 V; V
DS
= 28 V
V
GS
= 5.55 V; V
DS
= 10 V
V
GS
= 1.0 V; V
DS
= 0 V
[2]
[2]
[1]
[1]
65
1.6
1.9
-
-
-
-
65
1.7
1.9
-
-
-
-
-
2
2.6
1.5
-
5.4
-
-
2.1
2.6
1.5
-
1.05
-
-
2.45
3.3
-
1.4
-
140
-
2.55
3.2
-
1.4
-
140
V
V
V
%
A
A
nA
V
V
V
%
A
A
nA
Driver stage
V
(BR)DSS
drain-source breakdown voltage
V
GSq
gate-source quiescent voltage
Peaking section
Final stage
V
(BR)DSS
drain-source breakdown voltage
V
GSq
I
Dq
/T
I
DSS
I
DSX
I
GSS
gate-source quiescent voltage
quiescent drain current variation with temperature
drain leakage current
drain cut-off current
gate leakage current
V
GS
= 0 V; I
D
= 0.604 mA
V
DS
= 28 V; I
D
= 240 mA
V
DS
= 28 V; I
D
= 240 mA
T
case
=
40 C
to +85
C
V
GS
= 0 V; V
DS
= 28 V
V
GS
= 5.55 V; V
DS
= 10 V
V
GS
= 1.0 V; V
DS
= 0 V
All information provided in this document is subject to legal disclaimers.
65
1.6
[3]
[3]
-
2.15
3
2
-
11
-
-
2.6
3.8
-
1.4
-
140
V
V
V
%
A
A
nA
2
-
-
-
-
BLM7G1822S-80AB_S-80ABG
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 2 — 1 July 2015
4 of 18
NXP Semiconductors
BLM7G1822S-80AB(G)
LDMOS 2-stage power MMIC
Table 6.
DC characteristics
…continued
T
case
= 25
C; per section unless otherwise specified.
Symbol
Parameter
Conditions
V
GS
= 0 V; I
D
= 0.116 mA
V
DS
= 28 V; I
D
= 80 mA
V
DS
= 28 V; I
D
= 80 mA
I
Dq
/T
I
DSS
I
DSX
I
GSS
[1]
[2]
[3]
[4]
[4]
[4]
Min
65
1.7
2
-
-
-
-
Typ
-
2.15
2.7
2
-
1.9
-
Max
-
2.55
3.3
-
1.4
-
140
Unit
V
V
V
%
A
A
nA
Driver stage
V
(BR)DSS
drain-source breakdown voltage
V
GSq
gate-source quiescent voltage
quiescent drain current variation with temperature
drain leakage current
drain cut-off current
gate leakage current
T
case
=
40 C
to +85
C
V
GS
= 0 V; V
DS
= 28 V
V
GS
= 5.55 V; V
DS
= 10 V
V
GS
= 1.0 V; V
DS
= 0 V
In production circuit with 825
gate feed resistor.
In production circuit with 850
gate feed resistor.
In production circuit with 1205
gate feed resistor.
In production circuit with 460
gate feed resistor.
Table 7.
RF Characteristics
Typical RF performance at f = 2167.5 MHz; T
case
= 25
C; V
DS
= 28 V; I
Dq1
= 40 mA (carrier section, driver stage);
I
Dq2
= 120 mA (carrier section, final stage); P
L(AV)
= 4 W (carrier section); I
Dq1
= 80 mA (peaking section, driver stage);
I
Dq2
= 240 mA (peaking section, final stage); P
L(AV)
= 8 W (peaking section) unless otherwise specified, measured in an NXP
straight lead production circuit.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Carrier section
Test signal: single carrier W-CDMA
[1]
G
p
D
RL
in
ACPR
5M
PAR
O
power gain
drain efficiency
input return loss
adjacent channel power ratio (5 MHz)
output peak-to-average ratio
29.5
21
-
-
7
31
24
13.5
39.5
7.8
32.5
-
10
36.5
-
dB
%
dB
dBc
dB
Peaking section
Test signal: single carrier W-CDMA
[1]
G
p
D
RL
in
ACPR
5M
PAR
O
s21
s
21
2
[1]
[2]
power gain
drain efficiency
input return loss
adjacent channel power ratio (5 MHz)
output peak-to-average ratio
phase response difference
insertion power gain difference
normalized; between sections
normalized; between sections
26.8
20
-
-
5.2
15
0.6
28.3
24
20
36
7
-
-
29.8
-
10
31
-
+15
+0.6
dB
%
dB
dBc
dB
deg
dB
Test signal: CW
[2]
3GPP test model 1; 64 DPCH; PAR = 9.9 dB at 0.01% probability on CCDF.
f = 2170 MHz.
BLM7G1822S-80AB_S-80ABG
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 2 — 1 July 2015
5 of 18
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