IDT70V7288L20PFI8 datasheet, PDF

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IDT70V7288L20PFI8: DescriptionDual-Port SRAM, 64KX16, 20ns, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100; Categorystorage storage; File Size135KB，16 Pages; ManufacturerIDT (Integrated Device Technology)

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IDT70V7288L20PFI8 Overview

Dual-Port SRAM, 64KX16, 20ns, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100

IDT70V7288L20PFI8 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	QFP
package instruction	14 X 14 MM, 1.40 MM HEIGHT, TQFP-100
Contacts	100
Reach Compliance Code	not_compliant
ECCN code	3A991.B.2.B
Maximum access time	20 ns
JESD-30 code	S-PQFP-G100
JESD-609 code	e0
length	14 mm
memory density	1048576 bit
Memory IC Type	DUAL-PORT SRAM
memory width	16
Humidity sensitivity level	3
Number of functions	1
Number of terminals	100
word count	65536 words
character code	64000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	64KX16
Package body material	PLASTIC/EPOXY
encapsulated code	LFQFP
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	240
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum supply voltage (Vsup)	3.465 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	20
width	14 mm

IDT70V7288L20PFI8 Preview

HIGH-SPEED 3.3V

64K x 16 BANK-SWITCHABLE

DUAL-PORTED SRAM WITH

EXTERNAL BANK SELECTS

Features

IDT70V7288S/L

64K x 16 Bank-Switchable Dual-Ported SRAM Architecture

– Four independent 16K x 16 banks

– 1 Megabit of memory on chip

Fast asynchronous address-to-data access time: 15ns

User-controlled input pins included for bank selects

Independent port controls with asynchronous address & data

busses

Four 16-bit mailboxes available to each port for inter-

processor communications; interrupt option

Interrupt flags with programmable masking

Dual Chip Enables allow for depth expansion without

external logic

and

are available for x8 or x16 bus matching

LVTTL-compatible, single 3.3V (±5%) power supply

Available in a 100-pin Thin Quad Flatpack (14mm x 14mm)

Industrial temperature range (-40°C to +85°C) is available

for selected speeds

Functional Block Diagram

MUX

R/W

16Kx16

MEMORY

ARRAY

(BANK 0)

MUX

I/O

8L-15L

I/O

0L-7L

I/O

CONTROL

MUX

16Kx16

MEMORY

ARRAY

(BANK 1)

MUX

I/O

CONTROL

I/O

8R-15R

I/O

0R-7R

R/W

CONTROL

LOGIC

CONTROL

LOGIC

13L

0L(1)

ADDRESS

DECODE

ADDRESS

DECODE

13R

0R(1)

BANK

DECODE

MUX

16Kx16

MEMORY

ARRAY

(BANK 3)

MUX

BANK

DECODE

BKSEL

3(2)

BKSEL

0(2)

BANK

SELECT

5L(1)

0L(1)

/UB

R/W

MAILBOX

INTERRUPT

LOGIC

5R(1)

0R(1)

/UB

R/W

MBSEL

INT

MBSEL

INT

4077 drw 01

NOTES:

1. The first six address pins for each port serve dual functions. When

MBSEL

= V

, the pins serve as memory address inputs. When

MBSEL

= V

, the pins serve as mailbox

address inputs.

2. Each bank has an input pin assigned that allows the user to toggle the assignment of that bank between the two ports. Refer to Truth Table I for more details.

JUNE 2000

DSC-4077/6

IDT70V7288S/L

64K x 16 3.3V Bank-Switchable Dual-Ported SRAM with External Bank Selects

Industrial and Commercial Temperature Ranges

Description

The IDT70V7288 is a high-speed 64K x 16 (1M bit) Bank-Switch-

able Dual-Ported SRAM organized into four independent 16K x 16

banks. The device has two independent ports with separate controls,

addresses, and I/O pins for each port, allowing each port to asynchro-

nously access any 16K x 16 memory block not already accessed by the

other port. Accesses by the ports into specific banks are controlled via

bank select pin inputs under the user's control. Mailboxes are provided

to allow inter-processor communications. Interrupts are provided to

indicate mailbox writes have occurred. An automatic power down

feature controlled by the chip enables (CE

and CE

) permits the on-

chip circuitry of each port to enter a very low standby power mode and

allows fast depth expansion.

The IDT70V7288 offers a maximum address-to-data access time

as fast as 15ns, and is packaged in a 100-pin Thin Quad Flatpack

(TQFP).

the right port (See Truth Table IV). Once a bank is assigned to a

particular port, the port has full access to read and write within that

bank. Each port can be assigned as many banks within the array as

needed, up to and including all four banks.

The IDT70V7288 provides mailboxes to allow inter-processor

communications. Each port has four 16-bit mailbox registers available

to which it can write and read and which the opposite port can read

only. These mailboxes are external to the common SRAM array, and

are accessed by setting

MBSEL

= V

while setting

= V

. Each

mailbox has an associated interrupt: a port can generate an interrupt

to the opposite port by writing to the upper byte of any one of its four

16-bit mailboxes. The interrupted port can clear the interrupt by

reading the upper byte. This read will not alter the contents of the

mailbox.

If desired, any source of interrupt can be independently masked via

software. Two registers are provided to permit interpretation of inter-

rupts: the Interrupt Cause Register and the Interrupt Status Register.

The Interrupt Cause Register gives the user a snapshot of what has

caused the interrupt to be generated - the specific mailbox written to.

The information in this register provides post-mask signals: Interrupt

sources that have been masked will not be updated. The Interrupt

Status Register gives the user the status of all bits that could potentially

cause an interrupt regardless of whether they have been masked.

Truth Table V gives a detailed explanation of the use of these registers.

Functionality

The IDT70V7288 is a high-speed asynchronous 64K x 16 Bank-

Switchable Dual-Ported SRAM, organized in four 16K x 16 banks. The

two ports are permitted independent, simultaneous access into sepa-

rate banks within the shared array. There are four user-controlled

Bank Select input pins, and each of these pins is associated with a

specific bank within the memory array. Access to a specific bank is

gained by placing the associated Bank Select pin in the appropriate

state: V

assigns the bank to the left port, and V

assigns the bank to

6.42

IDT70V7288S/L

64K x 16 3.3V Bank-Switchable Dual-Ported SRAM with External Bank Selects

Industrial and Commercial Temperature Ranges

Pin Configurations

(1,2,3)

INDEX

10L

11L

13L

BKSEL

MBSEL

Vcc

R/W

GND

I/O

15L

I/O

14L

I/O

13L

I/O

12L

I/O

11L

I/O

10L

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76

12L

BKSEL

INT

GND

INT

BKSEL

12R

IDT70V7288PF

PN100-1(4)

100-Pin TQFP

Top View(5)

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

10R

11R

13R

BKSEL

MBSEL

GND

R/W

GND

I/O

15R

I/O

14R

I/O

13R

I/O

12R

I/O

11R

I/O

10R

4077 drw 02

NOTES:

1. All V

pins must be connected to power supply.

2. All GND pins must be connected to ground supply.

3. Package body is approximately 14mm x 14mm x 1.4mm.

4. This package code is used to reference the package diagram.

5. This text does not indicate orientation of the actual part-marking.

I/O

Vcc

I/O

GND

I/O1

I/O

GND

I/O

Vcc

I/O

Pin Names

- A

(1,6)

- BA

(1)

MBSEL

(1)

BKSEL

0-3

(2)

R/W

(1)

, CE

(1)

UB, LB

(1)

I/O

- I/O

(1)

INT

(1)

(4)

GND

(5)

Address Inputs

Bank Address Inputs

Mailbox Access Control Gate

Bank Select Inputs

Read/Write Enable

Output Enable

Chip Enables

I/O Byte Enables

Bidirectional Data Input/Output

Interrupt Flag (Output)

(3)

3.3VPower

Ground

4077 tbl 01

NOTES:

1. Duplicated per port.

2. Each bank has an input pin assigned that allows the user to toggle the assign-

ment of that bank between the two ports. Refer to Truth Table IV for more details.

When changing the bank assignments, accesses of the affected banks must

be suspended. Accesses may continue uninterrupted in banks that are not

being reallocated.

3. Generated upon mailbox access.

4. All Vcc pins must be connected to power supply.

5. All GND pins must be connected to ground supply.

6. The first six address pins (A

-A

) for each port serve dual functions. When MBSEL

= V

, the pins serve as memory address inputs. When MBSEL = V

, the pins serve

as mailbox address inputs (A

-A

ignored).

6.42

IDT70V7288S/L

64K x 16 3.3V Bank-Switchable Dual-Ported SRAM with External Bank Selects

Industrial and Commercial Temperature Ranges

Truth Table I Chip Enable

(1,2,3,4)

< 0.2V

-0.2V

<0.2V

Port Selected (TTL Active)

Port Selected (CMOS Active)

Port Deselected (TTL Inactive)

Port Deselected (CMOS Inactive)

4077 tbl 02

Mode

NOTES:

1. Chip Enable references are shown above with the actual

and CE

levels,

is a reference only.

2. Port "A" and "B" references are located where

is used.

3. "H" = V

and "L" = V

and

MBSEL

cannot be active at the same time.

Truth Table II Non-Contention Read/Write Control

Inputs

(1)

(2)

(3)

R/W

MBSEL

(3)

I/O

8-15

High-Z

DATA

High-Z

DATA

OUT

High-Z

DATA

OUT

High-Z

Outputs

I/O

0-7

High-Z

DATA

High-Z

DATA

OUT

DATA

OUT

High-Z

Mode

Deselected: Power-Down

Both Bytes Deselected

Write to Upper Byte Only

Write to Lower Byte Only

Write to Both Bytes

Read Upper Byte Only

Read Lower Byte Only

Read Both Bytes

Outputs Disabled

4077 tbl 03

NOTES:

1. BA

- BA

≠

- BA

: cannot access same bank simultaneously from both ports.

2. Refer to Truth Table I.

and

MBSEL

cannot both be active at the same time.

Truth Table III Mailbox Read/Write Control

(1)

Inputs

(2)

R/W

(3)

MBSEL

I/O

8-15

DATA

OUT

DATA

OUT

DATA

____

Outputs

I/O

0-7

DATA

OUT

DATA

OUT

DATA

____

Mode

Read Data from Mailbox,

↓

clears interrupt

Read Data from Mailbox,

↓

clears interrupt

Write Data into Mailbox

Not Allowed

4077 tbl 04

NOTES:

1. There are four mailbox locations per port written to and read from all the I/O's (I/O

-I/O

). These four mailboxes are addressed by A

-A

. Refer to Truth Table V.

2. Refer to Truth Table I.

3. Each mailbox location contains a 16-bit word, controllable in bytes by setting input levels to UB and LB appropriately.

6.42

IDT70V7288S/L

64K x 16 3.3V Bank-Switchable Dual-Ported SRAM with External Bank Selects

Industrial and Commercial Temperature Ranges

Absolute Maximum Ratings

(1)

Symbol

TERM

(2)

Rating

Terminal Voltage

with Respect

to GND

Temperature

Under Bias

Storage

Temperature

DC Output

Current

Commercial

& Industrial

-0.5 to +4.6

Unit

Maximum Operating Temperature

and Supply Voltage

(1)

Grade

Commercial

Ambient

Temperature

C to +70

-40

C to +85

GND

Vcc

3.3V

4077 tbl 06

BIAS

STG

OUT

-55 to +125

-65 to +150

Industrial

NOTES:

1. This is the parameter T

. This is the "instant on" case temperature.

4077 tbl 05

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may

cause permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those indicated in

the operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect reliability.

2. V

TERM

must not exceed Vcc + 5% for more than 25% of the cycle time or 10ns

maximum, and is limited to < 20mA for the period of V

TERM

> Vcc + 5%.

Recommended DC Operating

Conditions

Symbol

GND

Parameter

Supply Voltage

Ground

Input High Voltage

Input Low Voltage

Min.

3.135

2.0

-0.3

(1)

Typ.

3.3

____

Max.

3.465

+5%

(2)

0.8

Unit

4077 tbl 07

Capacitance

(1)

Symbol

OUT

(3)

Parameter

Input Capacitance

(TA = +25°C, f = 1.0mhz) TQFP Package

Conditions

(2)

= 3dV

OUT

= 3dV

Max.

Unit

4077 tbl 08

NOTES:

1. V

> -1.5V for pulse width less than 10ns.

2. V

TERM

must not exceed Vcc + 5%.

Output Capacitance

NOTES:

1. This parameter is determined by device characterization but is not production

tested.

2. 3dV represents the interpolated capacitance when the input and output signals

switch from 0V to 3V or from 3V to 0V.

3. C

OUT

represents C

I/O

as well.

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range

= 3.3V ± 5%)

70V7288S

Symbol

Parameter

Input Leakage Current

(1)

Output Leakage Current

Output Low Voltage

Output High Voltage

Test Conditions

= 3.465V, V

= 0V to V

= V

MBSEL

= V

, V

OUT

= 0V to V

= +4mA

= -4mA

Min.

___

70V7288L

Min.

___

Max.

0.4

___

Max.

0.4

___

Unit

µA

4077 tbl 09

___

2.4

NOTE:

1. At Vcc

2.0V, input leakages are undefined.

6.42

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