24C01C
1K 5.0V I
2
C™ Serial EEPROM
Features:
• Single Supply with Operation from 4.5V to 5.5V
• Low-Power CMOS Technology:
- Read current 1 mA, max.
- Standby current 5
A,
max.
• 2-Wire Serial Interface, I
2
C™ Compatible
• Cascadable up to Eight Devices
• Schmitt Trigger Inputs for Noise Suppression
• Output Slope Control to Eliminate Ground Bounce
• 100 kHz and 400 kHz Clock Compatibility
• Page Write Time 1 ms max.
• Self-Timed Erase/Write Cycle
• 16-Byte Page Write Buffer
• ESD Protection >4000V
• More than 1 Million Erase/Write Cycles
• Data Retention >200 Years
• Factory Programming Available
• Packages include 8-lead PDIP, SOIC, TSSOP,
DFN, TDFN, MSOP and 6-lead SOT-23
• Pb-Free and RoHS Compliant
• Temperature Ranges:
- Industrial (I):
-40C to +85C
- Automotive (E):
-40C to +125C
Description:
The Microchip Technology Inc. 24C01C is a 1K bit
Serial Electrically Erasable PROM with a voltage range
of 4.5V to 5.5V. The device is organized as a single
block of 128 x 8-bit memory with a 2-wire serial
interface. Low-current design permits operation with
max. standby and active currents of only 5
A
and 1
mA, respectively. The device has a page write capabil-
ity for up to 16 bytes of data and has fast write cycle
times of only 1 ms for both byte and page writes. Func-
tional address lines allow the connection of up to eight
24C01C devices on the same bus for up to 8K bits of
contiguous EEPROM memory. The device is available
in the standard 8-pin PDIP, 8-pin SOIC (3.90 mm),
8-pin 2x3 DFN and TDFN, 8-pin MSOP and TSSOP
packages. The 24C01C is also available in the 6-lead
SOT-23 package.
Block Diagram
A0 A1 A2
HV Generator
Memory
Control
Logic
I/O
Control
Logic
XDEC
EEPROM
Array
SDA SCL
V
CC
V
SS
Sense Amp.
R/W Control
YDEC
Package Types
PDIP, MSOP
A0
A1
A2
V
SS
1
2
3
4
8
7
6
5
V
CC
Test
SCL
SDA
A0
A1
A2
V
SS
SOIC, TSSOP
1
2
3
4
8
7
6
5
V
CC
Test
SCL
SDA
DFN/TDFN
A0 1
A1 2
A2 3
V
SS
4
8 V
CC
7 Test
6 SCL
5 SDA
SCL
V
SS
SDA
SOT-23
1
2
3
6
5
4
V
CC
A0
A1
1997-2012 Microchip Technology Inc.
DS21201K-page 1
24C01C
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(†)
V
CC
.............................................................................................................................................................................7.0V
All inputs and outputs w.r.t. V
SS
......................................................................................................... -0.6V to V
CC
+1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied ................................................................................................-40°C to +125°C
ESD protection on all pins
4 kV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
Electrical Characteristics:
Industrial (I):
V
CC
= +4.5V to 5.5V
Automotive (E): V
CC
= +4.5V to 5.5V
Min.
—
0.7 V
CC
—
0.05 V
CC
Max.
—
—
0.3 V
CC
—
Units
—
V
V
V
—
—
—
(Note)
T
A
= -40°C to +85°C
T
A
= -40°C to +125°C
Conditions
DC CHARACTERISTICS
Param.
No.
D1
D2
D3
D4
Sym.
—
V
IH
V
IL
V
HYS
Characteristic
A0, A1, A2, SCL, SDA
and WP pins:
High-level input voltage
Low-level input voltage
Hysteresis of Schmitt
Trigger inputs
(SDA, SCL pins)
Low-level output voltage
Input leakage current
Output leakage current
Pin capacitance
(all inputs/outputs)
D5
D6
D7
D8
D9
D10
Note:
V
OL
I
LI
I
LO
C
IN
,
C
OUT
I
CC
Write
I
CCS
—
—
—
—
—
—
—
0.40
±1
±1
10
1
3
5
V
A
A
pF
mA
mA
A
I
OL
= 3.0 mA @ V
CC
= 4.5V
V
IN
= V
SS
or V
CC
, WP = V
SS
V
OUT
= V
SS
or V
CC
V
CC
= 5.0V
(Note)
T
A
= 25°C, f = 1 MHz
V
CC
= 5.5V, SCL = 400 kHz
V
CC
= 5.5V
V
CC
= 5.5V, SDA = SCL = V
CC
WP = V
SS
I
CC
Read Operating current
Standby current
This parameter is periodically sampled and not 100% tested.
DS21201K-page 2
1997-2012 Microchip Technology Inc.
24C01C
TABLE 1-2:
AC CHARACTERISTICS
Electrical Characteristics:
Industrial (I):
V
CC
= +4.5V to 5.5V
Automotive (E): V
CC
= +4.5V to 5.5V
Characteristic
Clock frequency
Clock high time
Clock low time
SDA and SCL rise time
(Note
1)
SDA and SCL fall time
(Note
1)
Min.
—
—
4000
600
4700
1300
—
—
—
4000
600
4700
600
0
250
100
4000
600
—
—
4700
1300
10 + 0.1CB
Max.
100
400
—
—
—
—
1000
300
300
—
—
—
—
—
—
—
—
—
3500
900
—
—
250
Units
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
(I-temp)
—
(I-temp)
—
(I-temp)
—
(I-temp)
—
—
(I-temp)
—
(I-temp)
(Note
2)
—
(I-temp)
—
(I-temp)
—
(I-temp)
—
(I-temp)
(Note
1)
T
A
= -40°C to +85°C
T
A
= -40°C to +125°C
Conditions
AC CHARACTERISTICS
Param.
No.
1
2
3
4
5
6
7
8
9
10
11
12
Sym.
F
CLK
T
HIGH
T
LOW
T
R
T
F
T
HD
:
STA
Start condition hold time
T
SU
:
STA
Start condition setup time
T
HD
:
DAT
Data input hold time
T
SU
:
DAT
Data input setup time
T
SU
:
STO
Stop condition setup time
T
AA
T
BUF
Output valid from clock
(Note
2)
Bus free time: Time the bus
must be free before a new
transmission can start
Output fall time from V
IH
minimum to V
IL
maximum
C
B
100 pF
Input filter spike suppression
(SDA and SCL pins)
Write cycle time (byte or
page)
Endurance
13
T
OF
ns
14
15
16
Note 1:
2:
3:
4:
T
SP
T
WC
—
—
—
1,000,000
50
1.5
1
—
ns
ms
(Note
3)
—
(I-temp)
cycles 25°C
(Note
4)
Not 100% tested. C
B
= total capacitance of one bus line in pF.
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
The combined T
SP
and V
HYS
specifications are due to new Schmitt Trigger inputs, which provide improved
noise spike suppression. This eliminates the need for a T
I
specification for standard operation.
This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model, which can be obtained from Microchip’s web site
at www.microchip.com.
1997-2012 Microchip Technology Inc.
DS21201K-page 3
24C01C
FIGURE 1-1:
BUS TIMING DATA
5
2
D4
4
SCL
SDA
IN
7
6
14
3
8
9
10
11
SDA
OUT
12
DS21201K-page 4
1997-2012 Microchip Technology Inc.
24C01C
2.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in
Table 2-1.
TABLE 2-1:
Name
A0
A1
A2
V
SS
SDA
SCL
Test
V
CC
PIN FUNCTION TABLE
8-pin
PDIP
1
2
3
4
5
6
7
8
8-pin
SOIC
1
2
3
4
5
6
7
8
8-pin
TSSOP
1
2
3
4
5
6
7
8
8-pin
MSOP
1
2
3
4
5
6
7
8
8-pin
DFN/TDFN
1
2
3
4
5
6
7
8
SOT-23
5
4
—
2
3
1
—
6
Function
Chip Select
Chip Select
Chip Select
Ground
Serial Data
Serial Clock
Test
+4.5V to 5.5V Power Supply
2.1
SDA Serial Data
2.5
Noise Protection
This is a bidirectional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal; therefore, the SDA bus requires a pull-
up resistor to V
CC
(typical 10 k for 100 kHz, 2 k for
400 kHz).
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
The 24C01C employs a V
CC
threshold detector circuit
which disables the internal erase/write logic if the V
CC
is below 3.8 volts at nominal conditions.
The SCL and SDA inputs have Schmitt Trigger and
filter circuits which suppress noise spikes to assure
proper device operation even on a noisy bus.
2.2
SCL Serial Clock
This input is used to synchronize the data transfer from
and to the device.
2.3
A0, A1, A2
The levels on these inputs are compared with the
corresponding bits in the slave address. The chip is
selected if the compare is true.
Up to eight 24C01C devices may be connected to the
same bus by using different Chip Select bit combina-
tions. These inputs must be connected to either V
CC
or
V
SS
.
For the SOT-23 devices up to four devices may be con-
nected to the same bus using different Chip Select bit
combinations.
In most applications, the chip address inputs A0, A1
and A2 are hard-wired to logic ‘0’ or logic ‘1’. For
applications in which these pins are controlled by a
microcontroller or other programmable device, the chip
address pins must be driven to logic ‘0’ or logic ‘1’
before normal device operation can proceed.
2.4
Test
This pin is utilized for testing purposes only. It may be
tied high, tied low or left floating.
1997-2012 Microchip Technology Inc.
DS21201K-page 5
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