EPF10K50EFC256-1 datasheet, PDF

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EPF10K50EFC256-1: DescriptionLoadable PLD, 0.5ns, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, FINE LINE, BGA-256; CategoryProgrammable logic devices Programmable logic; File Size2MB，110 Pages; ManufacturerIntel; Websitehttp://www.intel.com/

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EPF10K50EFC256-1 Overview

Loadable PLD, 0.5ns, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, FINE LINE, BGA-256

EPF10K50EFC256-1 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Intel
package instruction	BGA, BGA256,16X16,40
Reach Compliance Code	compliant
ECCN code	3A991
Other features	2880 LOGIC ELEMENTS
maximum clock frequency	140 MHz
JESD-30 code	S-PBGA-B256
JESD-609 code	e0
length	17 mm
Humidity sensitivity level	3
Number of I/O lines	191
Number of entries	191
Number of logical units	2880
Output times	191
Number of terminals	256
Maximum operating temperature	70 °C
Minimum operating temperature
organize	191 I/O
Output function	MIXED
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA256,16X16,40
Package shape	SQUARE
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	220
power supply	2.5,2.5/3.3 V
Programmable logic type	LOADABLE PLD
propagation delay	0.5 ns
Certification status	Not Qualified
Maximum seat height	2.1 mm
Maximum supply voltage	2.7 V
Minimum supply voltage	2.3 V
Nominal supply voltage	2.5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
width	17 mm

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FLEX 10KE

Embedded Programmable

Logic Device

Data Sheet

January 2003, ver. 2.5

Features...

■

Embedded programmable logic devices (PLDs), providing

system-on-a-programmable-chip (SOPC) integration in a single

device

–

Enhanced embedded array for implementing megafunctions

such as efficient memory and specialized logic functions

–

Dual-port capability with up to 16-bit width per embedded array

block (EAB)

–

Logic array for general logic functions

High density

–

30,000 to 200,000 typical gates (see

Tables 1

and

–

Up to 98,304 RAM bits (4,096 bits per EAB), all of which can be

used without reducing logic capacity

System-level features

–

MultiVolt

I/O pins can drive or be driven by 2.5-V, 3.3-V, or

5.0-V devices

–

Low power consumption

–

Bidirectional I/O performance (t

and

) up to 212 MHz

–

Fully compliant with the PCI Special Interest Group (PCI SIG)

PCI Local Bus Specification, Revision 2.2

for 3.3-V operation at

33 MHz or 66 MHz

–

-1 speed grade devices are compliant with

PCI Local Bus

Specification, Revision 2.2,

for 5.0-V operation

–

Built-in Joint Test Action Group (JTAG) boundary-scan test

(BST) circuitry compliant with IEEE Std. 1149.1-1990, available

without consuming additional device logic

For information on 5.0-V FLEX

10K or 3.3-V FLEX 10KA devices, see the

FLEX 10K Embedded Programmable Logic Family Data Sheet.

Table 1. FLEX 10KE Device Features

Feature

Typical gates

(1)

Maximum system gates

Logic elements (LEs)

EABs

Total RAM bits

Maximum user I/O pins

Altera Corporation

DS-F10KE-2.5

EPF10K30E

30,000

119,000

1,728

24,576

220

EPF10K50E

EPF10K50S

50,000

199,000

2,880

40,960

254

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