CY7C1370D
CY7C1372D
18-Mbit (512 K × 36/1 M × 18) Pipelined
SRAM with NoBL™ Architecture
18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM with NoBL™ Architecture
Features
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Functional Description
The CY7C1370D and CY7C1372D are 3.3 V, 512 K × 36 and
1 M × 18 synchronous pipelined burst SRAMs with No Bus
Latency™ (NoBL logic, respectively. They are designed to
support unlimited true back-to-back read/write operations with
no wait states. The CY7C1370D and CY7C1372D are equipped
with the advanced (NoBL) logic required to enable consecutive
read/write operations with data being transferred on every clock
cycle. This feature dramatically improves the throughput of data
in systems that require frequent write/read transitions. The
CY7C1370D and CY7C1372D are pin compatible and
functionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. The clock
input is qualified by the clock enable (CEN) signal, which when
deasserted suspends operation and extends the previous clock
cycle.
Write operations are controlled by the byte write selects
(BW
a
–BW
d
for CY7C1370D and BW
a
–BW
b
for CY7C1372D)
and a write enable (WE) input. All writes are conducted with
on-chip synchronous self-timed write circuitry.
Three synchronous chip enables (CE
1
, CE
2
, CE
3
) and an
asynchronous output enable (OE) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tristated during
the data portion of a write sequence.
Pin-compatible and functionally equivalent to ZBT™
Supports 250-MHz bus operations with zero wait states
❐
Available speed grades are 250, 200, and 167 MHz
Internally self-timed output buffer control to eliminate the need
to use asynchronous OE
Fully registered (inputs and outputs) for pipelined operation
Byte write capability
3.3 V core power supply (V
DD
)
3.3 V/2.5 V I/O power supply (V
DDQ
)
Fast clock-to-output times
❐
2.6 ns (for 250 MHz device)
Clock enable (CEN) pin to suspend operation
Synchronous self-timed writes
Available in JEDEC-standard Pb-free 100-pin TQFP, Pb-free
and non Pb-free 65-ball FBGA package
IEEE 1149.1 JTAG-compatible boundary scan
Burst capability – linear or interleaved burst order
“ZZ” sleep mode option and stop clock option
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Selection Guide
Description
Maximum access time
Maximum operating current
Maximum CMOS standby current
250 MHz
2.6
350
70
200 MHz
3.0
300
70
167 MHz
3.4
275
70
Unit
ns
mA
mA
Errata:
For information on silicon errata, see
“Errata”
on page 30. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation
Document Number: 38-05555 Rev. *Q
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised October 9, 2013
CY7C1370D
CY7C1372D
Contents
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 6
Functional Overview ........................................................ 8
Single Read Accesses ................................................ 8
Burst Read Accesses .................................................. 8
Single Write Accesses ................................................. 8
Burst Write Accesses .................................................. 8
Sleep Mode ................................................................. 9
Interleaved Burst Address Table ................................. 9
Linear Burst Address Table ......................................... 9
ZZ Mode Electrical Characteristics .............................. 9
Truth Table ...................................................................... 10
Partial Write Cycle Description ..................................... 11
IEEE 1149.1 Serial Boundary Scan (JTAG [17]) ........... 12
Disabling the JTAG Feature ...................................... 12
Test Access Port (TAP) ............................................. 12
PERFORMING A TAP RESET .................................. 12
TAP REGISTERS ...................................................... 12
TAP Instruction Set ................................................... 13
TAP Controller State Diagram ....................................... 14
TAP Controller Block Diagram ...................................... 15
TAP Timing ...................................................................... 15
TAP AC Switching Characteristics ............................... 16
3.3 V TAP AC Test Conditions ....................................... 17
3.3 V TAP AC Output Load Equivalent ......................... 17
2.5 V TAP AC Test Conditions ....................................... 17
2.5 V TAP AC Output Load Equivalent ......................... 17
TAP DC Electrical Characteristics and
Operating Conditions ..................................................... 17
Identification Register Definitions ................................ 18
Scan Register Sizes ....................................................... 18
Identification Codes ....................................................... 18
Boundary Scan Order .................................................... 19
Maximum Ratings ........................................................... 20
Operating Range ............................................................. 20
Neutron Soft Error Immunity ......................................... 20
Electrical Characteristics ............................................... 20
Capacitance .................................................................... 21
Thermal Resistance ........................................................ 21
AC Test Loads and Waveforms ..................................... 22
Switching Characteristics .............................................. 23
Switching Waveforms .................................................... 24
Ordering Information ...................................................... 26
Ordering Code Definitions ......................................... 26
Package Diagrams .......................................................... 27
Acronyms ........................................................................ 29
Document Conventions ................................................. 29
Units of Measure ....................................................... 29
Errata ............................................................................... 30
Part Numbers Affected .............................................. 30
Product Status ........................................................... 30
Ram9 NoBL ZZ Pin & JTAG Issues
Errata Summary ............................................................... 30
Document History Page ................................................. 32
Sales, Solutions, and Legal Information ...................... 34
Worldwide Sales and Design Support ....................... 34
Products .................................................................... 34
PSoC® Solutions ...................................................... 34
Cypress Developer Community ................................. 34
Technical Support ..................................................... 34
Document Number: 38-05555 Rev. *Q
Page 3 of 34
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