1 GSPS 8-BIT A/D CONVERTER
TS8388BFS
DESCRIPTION
The TS8388BFS is a monolithic 8–bit analog–to–digital converter, designed for digitizing wide bandwidth analog signals at very high sampling
rates of up to 1 GSPS.
The TS8388BFS is using an innovative architecture, including an on chip Sample and Hold (S/H), and is fabricated with an advanced high
speed bipolar process (B6HF from Siemens).
The on–chip S/H has a 2 GHz full power input bandwidth, providing excellent dynamic performance in undersampling applications (High IF
digitizing).
MAIN FEATURES
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8-bit resolution.
ADC gain adjust.
1.5 GHz full power input bandwidth.
1 GSPS (min) sampling rate.
SINAD = 44.3 dB (7.2 Effective Bits) SFDR = 58 dBc
@ F
S
= 1 GSPS, F
IN
= 20 MHz :
SINAD = 42.9 dB (7.0 Effective Bits) SFDR = 52 dBc
@ F
S
= 1 GSPS, F
IN
= 500 MHz :
SINAD = 40.3dB (6.8 Effective Bits) SFDR = 50 dBc
@ F
S
= 1 GSPS, F
IN
= 1000 MHz (-3 dB FS)
2-tone IMD : -52dBc (489 MHz, 490 MHz) @ 1GSPS.
DNL = 0.4 LSB
INL = 0.7 LSB.
Low Bit Error Rate (10
-13
) @ 1 GSPS
Very low input capacitance : 3 pF
500 mVpp differential or single-ended analog inputs.
Differential or single-ended 50
Ω
ECL compatible
clock inputs.
ECL or LVDS/HSTL output compatibility.
Data ready output with asynchronous reset.
Gray or Binary selectable output data ; NRZ output mode.
Power consumption :
3.6 W @ Tj = 70°C
3.8 W @ Tj =125°C
FS Suffix
Rth CQFP 68
Ceramic Quad Flat Pack
1/ Die form : JTS8388B
2/ Evaluation board : TSEV8388BF
3/ Dmux TS81102G0 : companion device available
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CQFP package enhanced with heat spreader : Rthjc = 4.75°C/W
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Dual power supply : ± 5 V
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Radiation tolerance oriented design
(150 Krad (Si) measured).
APPLICATIONS
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Digital Sampling Oscilloscopes.
Satellite receiver.
Electronic countermeasures / Electronic warfare.
Direct RF down – conversion.
SCREENING
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TCS standard screening level
Mil-PRF-38535, QML level Q for package version.
Space screening according to ESA/SCC 9000.
Temperature range : -55°C < Tc ; Tj < +125°C
May 2000
TS8388BFS
Preliminary Beta Site
TABLE OF CONTENTS
1.
2.
3.
SIMPLIFIED BLOCK DIAGRAM ....................................................................................................................................3
FUNCTIONAL DESCRIPTION.........................................................................................................................................3
SPECIFICATIONS ..............................................................................................................................................................4
3.1.
3.2.
3.3.
3.4.
3.5.
3.6.
3.7.
3.8.
ABSOLUTE MAXIMUM RATINGS (
SEE NOTES BELOW
) ....................................................................................................................... 4
R
ECOMMENDED CONDITIONS OF USE
...................................................................................................................................................... 4
ELECTRICAL OPERATING CHARACTERISTICS.............................................................................................................................. 5
T
IMING
D
IAGRAMS
................................................................................................................................................................................ 9
EXPLANATION OF TEST LEVELS................................................................................................................................................... 10
WAFER SCREENING....................................................................................................................................................................... 10
FUNCTIONS DESCRIPTION............................................................................................................................................................ 11
DIGITAL OUTPUT CODING ............................................................................................................................................................. 11
TS8388BFS PIN DESCRIPTION ...................................................................................................................................................... 12
TS8388BFS PINOUT........................................................................................................................................................................ 13
OUTLINE DIMENSIONS – 68
PINS
CQFP......................................................................................................................................... 14
THERMAL CHARACTERISTICS ...................................................................................................................................................... 15
STATIC LINEARITY – FS = 50 MSPS / FIN = 10 MH
Z
...................................................................................................................... 16
EFFECTIVE NUMBER OF BITS VERSUS POWER SUPPLIES VARIATION ................................................................................... 17
TYPICAL FFT RESULTS .................................................................................................................................................................. 18
SPURIOUS FREE DYNAMIC RANGE VERSUS INPUT AMPLITUDE .............................................................................................. 19
DYNAMIC PERFORMANCE VERSUS ANALOG INPUT FREQUENCY ........................................................................................... 20
EFFECTIVE NUMBER OF BITS (ENOB) VERSUS SAMPLING FREQUENCY ................................................................................ 20
SFDR VERSUS SAMPLING FREQUENCY ...................................................................................................................................... 21
TS8388BFS ADC PERFORMANCES VERSUS JUNCTION TEMPERATURE ................................................................................. 22
TYPICAL FULL POWER INPUT BANDWIDTH ................................................................................................................................. 23
ADC STEP RESPONSE............................................................................................................................................................... 24
4.
PACKAGE DESCRIPTION. ............................................................................................................................................12
4.1.
4.2.
4.3.
4.4.
5.
TYPICAL CHARACTERIZATION RESULTS .............................................................................................................16
5.1.
5.2.
5.3.
5.4.
5.5.
5.6.
5.7.
5.8.
5.9.
5.10.
6.
7.
DEFINITION OF TERMS ................................................................................................................................................25
APPLYING THE TS8388BFS...........................................................................................................................................27
7.1.
7.2.
7.3.
7.4.
7.5.
7.6.
7.7.
7.8.
7.9.
7.10.
7.11.
TIMING INFORMATIONS ................................................................................................................................................................. 27
PRINCIPLE OF DATA READY SIGNAL CONTROL BY DRRB INPUT COMMAND .......................................................................... 28
ANALOG INPUTS (VIN) (VINB) ........................................................................................................................................................ 29
CLOCK INPUTS (CLK) (CLKB)......................................................................................................................................................... 30
CLOCK SIGNAL DUTY CYCLE ADJUST ......................................................................................................................................... 31
NOISE IMMUNITY INFORMATIONS ................................................................................................................................................ 31
DIGITAL OUTPUTS.......................................................................................................................................................................... 32
OUT OF RANGE BIT ........................................................................................................................................................................ 35
GRAY OR BINARY OUTPUT DATA FORMAT SELECT................................................................................................................... 35
DIODE PIN 49 .............................................................................................................................................................................. 35
ADC GAIN CONTROL PIN 60 ...................................................................................................................................................... 36
EQUIVALENT ANALOG INPUT CIRCUIT AND ESD PROTECTIONS.............................................................................................. 37
EQUIVALENT ANALOG CLOCK INPUT CIRCUIT AND ESD PROTECTIONS................................................................................. 37
EQUIVALENT DATA OUTPUT BUFFER CIRCUIT AND ESD PROTECTIONS ................................................................................ 38
ADC GAIN ADJUST EQUIVALENT INPUT CIRCUITS AND ESD PROTECTIONS .......................................................................... 38
GORB EQUIVALENT INPUT SCHEMATIC AND ESD PROTECTIONS............................................................................................ 39
DRRB EQUIVALENT INPUT SCHEMATIC AND ESD PROTECTIONS ............................................................................................ 39
8.
EQUIVALENT INPUT / OUTPUT SCHEMATICS.......................................................................................................37
8.1.
8.2.
8.3.
8.4.
8.5.
8.6.
9.
10.
TSEV8388BF : CHIP EVALUATION BOARD (SEE SEPARATE TSEV8388BF SPECIFICATION)....................40
ORDERING INFORMATION......................................................................................................................................41
P
ACKAGE DEVICE
........................................................................................................................................................................... 41
E
VALUATION BOARD
....................................................................................................................................................................... 41
10.1.
10.2.
2
/
42
Preliminary Beta Site
TS8388BFS
1.
SIMPLIFIED BLOCK DIAGRAM
GAIN
MASTER/SLAVE TRACK & HOLD AMPLIFIER
VIN,VINB
G=2
T/H
G=1
T/H
G=1
RESISTOR
CHAIN
ANALOG
ENCODING
BLOCK
4
INTERPOLATION
STAGES
4
5
REGENERATION
LATCHES
4
ERROR CORRECTION &
DECODE LOGIC
CLK, CLKB
CLOCK
BUFFER
8
OUTPUT LATCHES &
BUFFERS
8
DRRB DR,DRB
GORB
DATA,DATAB
OR,ORB
5
2.
FUNCTIONAL DESCRIPTION
The TS8388BFS is an 8 bit 1GSPS ADC based on an advanced high speed bipolar technology (B6HF from SIEMENS) featuring a cutoff
frequency of 25 GHz.
The TS8388BFS includes a front-end master/slave Track and Hold stage (S/H), followed by an analog encoding stage and interpolation
circuitry.
Successive banks of latches are regenerating the analog residues into logical data before entering an error correction circuitry and a
resynchronization stage followed by 75
Ω
differential output buffers.
The TS8388BFS works in fully differential mode from analog inputs up to digital outputs.
The TS8388BFS features a full power input bandwidth of 1.5 GHz.
Control pin GORB is provided to select either Gray or Binary data output format.
Gain control pin is provided in order to adjust the ADC gain.
A Data Ready output asynchronous reset (DRRB) is available on TS8388BFS.
The TS8388BFS uses only vertical isolated NPN transistors together with oxide isolated polysilicon resistors, which allow enhanced radiation
tolerance (no performance drift measured at 150kRad total dose).
3/42
Preliminary Beta Site
TS8388BFS
3.3.
ELECTRICAL OPERATING CHARACTERISTICS
VEE = DVEE = -5 V ; V
CC
= +5 V ; V
IN
-V
INB
= 500 mVpp Full Scale differential input ;
Digital outputs 75 or 50
Ω
differentially terminated ;
Tj (typical) = 70°C. Full temperature range : -55°C < Tc ; Tj < +125°C
Parameter
Symb
Temp
Test
level
Min
Typ
Max
Unit
POWER REQUIREMENTS
Positive supply voltage
Analog
Digital (ECL)
Digital (LVDS)
Positive supply current
Analog
Digital
Negative supply voltage
Negative supply current
Nominal power dissipation
Power supply rejection ratio
RESOLUTION
ANALOG INPUTS
Full Scale Input Voltage range (differential mode)
( 0 Volt common mode voltage )
Full Scale Input Voltage range (single–ended input option )
(see Application Notes)
Analog input capacitance
Input bias current
Input Resistance
Full Power input Bandwidth
Small Signal input Bandwidth (10 % full scale)
CLOCK INPUTS
Logic compatibility for clock inputs
(see Application Notes)
ECL Clock inputs voltages (V
CLK
or V
CLKB
) :
•
•
•
•
Logic “0” voltage
Logic “1” voltage
Logic “0” current
Logic “1” current
V
IL
V
IH
I
IL
I
IH
-1.1
5
5
DBm into 50
Ω
Full
C
CLK
Full
IV
IV
-2
4
3
10
3.5
dBm
pF
(note 10 )
Full
IV
-1.5
V
V
µA
µA
ECL or specified clock input
power level in dBm
V
IN
V
INB
V
IN
V
INB
C
IN
I
IN
R
IN
FPBW
SSBW
Full
Full
Full
Full
Full
IV
IV
IV
IV
IV
0.5
1.3
1.5
Full
IV
Full
IV
-125
-125
-250
0
3
10
1
1.5
1.7
3.5
20
125
125
250
mV
mV
mV
mV
pF
µA
MΩ
GHz
GHz
(note 2)
Analog
Digital
VCC
V
PLUSD
V
PLUSD
ICC
I
PLUSD
VEE
AIEE
DIEE
PD
Full
PSRR
II
IV
IV
Full
IV
II,IV
-5.25
II, IV
1.4
II,IV
4.75
5
0
2.4
400
120
-5
170
140
3.6
3.8
+/- 0.5
8
2.6
425
130
-4.75
185
160
3.7
3.9
5.25
V
V
V
mA
mA
V
mA
mA
W
W
mV/V
bits
Clock input power level into 50
Ω
termination
Clock input power level
Clock input capacitance
5/42
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