8Mb
SMART 3 BOOT BLOCK FLASH MEMORY
FLASH MEMORY
MT28F008B3
MT28F800B3
3V Only, Dual Supply (Smart 3)
40-Pin TSOP Type I 48-Pin TSOP Type I
FEATURES
• Eleven erase blocks:
16KB/8K-word boot block (protected)
Two 8KB/4K-word parameter blocks
Eight main memory blocks
• Smart 3 technology (B3):
3.3V ±0.3V V
CC
3.3V ±0.3V V
PP
application programming
5V ±10% V
PP
application/production programming
12V ±5% V
PP
compatibility production
programming
• Address access time:
100ns
• 100,000 ERASE cycles
• Industry-standard pinouts
• Automated write and erase algorithm
• Two-cycle WRITE/ERASE sequence
• TSOP, SOP and FBGA packaging options
• Byte- or word-wide READ and WRITE (MT28F800B3):
1 Meg x 8/512K x 16
44-Pin SOP
GENERAL DESCRIPTION
OPTIONS
• Timing
100ns access
100ns access
• Configurations
1 Meg x 8
512K x 16/1 Meg x 8
• Boot Block Starting Word Address
Top
Bottom
• Operating Temperature Range
Commercial (0°C to +70°C)
Extended (-40°C to +85°C)
• Packages
Plastic 40-pin TSOP Type 1
(10mm x 20mm)
Plastic 48-pin TSOP Type 1
(12mm x 20mm)
Plastic 44-pin SOP
(600 mil)
Part Number Example:
MARKING
-10
-10 ET
MT28F008B3
MT28F800B3
T
B
None
ET
VG
WG
SG
MT28F800B3WG-10 BET
8Mb Smart 3 Boot Block Flash Memory
Q10.p65 – Rev.3/00
The MT28F008B3 (x8) and MT28F800B3 (x16/x8)
are low-voltage, nonvolatile, electrically block-erasable
(flash), programmable read-only memories containing
8,388,608 bits organized as 524,288 words (16 bits) or
1,048,576 bytes (8 bits). These devices are fabricated
with Micron’s advanced CMOS floating-gate process.
Depending on speed and temperature options, writing
or erasing the device can be done with a V
PP
voltage
ranging from 3.3V to 5V, and all operations can be done
with a V
CC
range from 3V to 3.6V. Due to process
technology advances, 5V V
PP
is optimal for application
and production programming. For backward compat-
ibility with SmartVoltage technology, 12V V
PP
is sup-
ported for a maximum of 100 cycles and may be
connected for up to 100 cumulative hours.
The MT28F008B3 and MT28F800B3 are organized
into eleven separately erasable blocks. To ensure that
critical firmware is protected from accidental erasure or
overwrite, the devices feature a hardware-protected
boot block. This block may be used to store code
implemented in low-level system recovery. The re-
maining blocks vary in density and are written and
erased with no additional security measures.
Please refer to Micron’s Web site (www.micron.com/
flash/htmls/datasheets.html)
for the latest data sheet.
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
8Mb
SMART 3 BOOT BLOCK FLASH MEMORY
PIN ASSIGNMENT (Top View)
48-Pin TSOP Type I
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RP#
V
PP
WP#
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE#
V
SS
DQ15/(A - 1)
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
V
SS
CE#
A0
V
PP
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE#
V
SS
OE#
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44-Pin SOP
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
RP#
WE#
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE#
V
SS
DQ15/(A - 1)
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
ORDER NUMBER AND PART MARKING
MT28F800B3WG-10 B
MT28F800B3WG-10 T
MT28F800B3WG-10 BET
MT28F800B3WG-10 TET
DQ3
DQ11
ORDER NUMBER AND PART MARKING
MT28F800B3SG-10 B
MT28F800B3SG-10 T
MT28F800B3SG-10 BET
MT28F800B3SG-10 TET
40-Pin TSOP Type I
A16
A15
A14
A13
A12
A11
A9
A8
WE#
RP#
V
PP
WP#
A18
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A17
V
SS
NC
A19
A10
DQ7
DQ6
DQ5
DQ4
V
CC
V
CC
NC
DQ3
DQ2
DQ1
DQ0
OE#
V
SS
CE#
A0
ORDER NUMBER AND PART MARKING
MT28F008B3VG-10 B
MT28F008B3VG-10 T
MT28F008B3VG-10 BET
MT28F008B3VG-10 TET
8Mb Smart 3 Boot Block Flash Memory
Q10.p65 – Rev.3/00
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
8Mb Smart 3 Boot Block Flash Memory
Q10.p65 – Rev.3/00
FUNCTIONAL BLOCK DIAGRAM
8
Input
Buffer
BYTE#
2
I/O
Control
Logic
16KB Boot Block
Addr.
7
Input
Buffer
A0-A18/(A19)
A9
Buffer/
Latch
19 (20)
10
8KB Parameter Block
8KB Parameter Block
96KB Main Block
128KB Main Block
128KB Main Block
128KB Main Block
128KB Main Block
128KB Main Block
128KB Main Block
128KB Main Block
16
Input Data
Latch/Mux
A-1
Input
Buffer
X - Decoder/Block Erase Control
9
(10)
Addr.
Power
(Current)
Control
Counter
DQ15/(A - 1)
2
DQ8-DQ14
2
WP#
1
CE#
OE#
WE#
RP#
V
CC
V
PP
V
PP
Switch/
Pump
Command
Execution
Logic
State
8Mb
SMART 3 BOOT BLOCK FLASH MEMORY
Machine
Y-
Decoder
7
Y - Select Gates
8
Sense Amplifiers
Write/Erase-Bit
Compare and Verify
DQ0-DQ7
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
Output
Buffer
DQ15
Status
Register
Identification
Register
7
Output
Buffer
8
Output
Buffer
MUX
8
NOTE:
1. Does not apply to MT28F800B3SG.
2. Does not apply to MT28F008B3.
8Mb
SMART 3 BOOT BLOCK FLASH MEMORY
PIN DESCRIPTIONS
40-PIN TSOP
NUMBERS
9
48-PIN TSOP
NUMBERS SYMBOL
11
WE#
TYPE
Input
DESCRIPTION
Write Enable: Determines if a given cycle is a WRITE cycle. If WE# is
LOW, the cycle is either a WRITE to the command execution logic
(CEL) or to the memory array.
Write Protect: Unlocks the boot block when HIGH if V
PP
= V
PPH
1
(3.3V) or V
PPH
2
(5V) and RP# = V
IH
during a WRITE or ERASE. Does
not affect WRITE or ERASE operation on other blocks.
Chip Enable: Activates the device when LOW. When CE# is HIGH,
the device is disabled and goes into standby power mode.
Reset/Power-Down: When LOW, RP# clears the status register, sets
the internal state machine (ISM) to the array read mode and places
the device in deep power-down mode. All inputs, including CE#,
are “Don’t Care,” and all outputs are High-Z. RP# unlocks the boot
block and overrides the condition of WP# when at V
HH
(12V), and
must be held at V
IH
during all other modes of operation.
Output Enable: Enables data output buffers when LOW. When
OE# is HIGH, the output buffers are disabled.
Byte Enable: If BYTE# = HIGH, the upper byte is active through
DQ8-DQ15. If BYTE# = LOW, DQ8-DQ14 are High-Z, and all data is
accessed through DQ0-DQ7. DQ15/(A - 1) becomes the least
significant address input.
Address Inputs: Select a unique 16-bit word or 8-bit byte. The
DQ15/(A - 1) input becomes the lowest order address when
BYTE# = LOW (MT28F800B3) to allow for a selection of an 8-bit
byte from the 1,048,576 available.
Data I/O: MSB of data when BYTE# = HIGH. Address Input: LSB
of address input when BYTE# = LOW during READ or WRITE
operation.
Data I/Os: Data output pins during any READ operation or data
input pins during a WRITE. These pins are used to input commands
to the CEL.
Data I/Os: Data output pins during any READ operation or data
input pins during a WRITE when BYTE# = HIGH. These pins are
High-Z when BYTE# is LOW.
Write/Erase Supply Voltage: From a WRITE or ERASE CONFIRM
until completion of the WRITE or ERASE, V
PP
must be at V
PPH
1
(3.3V), V
PPH
2
(5V) or V
PPH
3
(12V)
1
. V
PP
= “Don’t Care” during all
other operations.
Power Supply: +3.3V ±0.3V.
Ground.
No Connect: These pins may be driven or left unconnected.
12
14
WP#
Input
22
10
26
12
CE#
RP#
Input
Input
24
–
28
47
OE#
BYTE#
Input
Input
21, 20, 19, 18, 25, 24, 23,
17, 16, 15, 14, 22, 21, 20,
8, 7, 36, 6, 5, 19, 18, 8, 7,
4, 3, 2, 1, 40, 6, 5, 4, 3, 2,
13, 37
1, 48, 17, 16
–
45
A0-A18/
(A19)
Input
DQ15/
(A - 1)
DQ0-
DQ7
DQ8-
DQ14
V
PP
Input/
Output
Input/
Output
Input/
Output
Supply
25, 26, 27,
28, 32, 33,
34, 35
–
29, 31, 33,
35, 38, 40,
42, 44
30, 32, 34,
36, 39, 41,
43
13
11
30, 31
23, 39
29, 38
37
27, 46
9, 10, 15
V
CC
V
SS
NC
Supply
Supply
–
NOTE:
1. For SmartVoltage-compatible production programming, 12V V
PP
is supported for a maximum of 100 cycles and may be
connected for up to 100 cumulative hours.
(continued on next page)
8Mb Smart 3 Boot Block Flash Memory
Q10.p65 – Rev.3/00
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
8Mb
SMART 3 BOOT BLOCK FLASH MEMORY
PIN DESCRIPTIONS (continued)
44-PIN SOP
NUMBERS
43
SYMBOL
WE#
TYPE
Input
DESCRIPTION
Write Enable: Determines if a given cycle is a WRITE cycle. If WE# is LOW, the
cycle is either a WRITE to the command execution logic (CEL) or to the
memory array.
Chip Enable: Activates the device when LOW. When CE# is HIGH, the device is
disabled and goes into standby power mode.
Reset/Power-Down: When LOW, RP# clears the status register, sets the
internal state machine (ISM) to the array read mode and places the device in
deep power-down mode. All inputs, including CE#, are “Don’t Care,” and all
outputs are High-Z. RP# unlocks the boot block and overrides the condition
of WP# when at V
HH
(12V), and must be held at V
IH
during all other modes of
operation.
Output Enable: Enables data output buffers when LOW. When OE# is HIGH,
the output buffers are disabled.
Byte Enable: If BYTE# = HIGH, the upper byte is active through DQ8-DQ15. If
BYTE# = LOW, DQ8-DQ14 are High-Z, and all data is accessed through DQ0-
DQ7. DQ15/(A - 1) becomes the least significant address input.
Address Inputs: Select a unique 16-bit word or 8-bit byte. The DQ15/(A - 1)
input becomes the lowest order address when BYTE# = LOW (MT28F800B3)
to allow for a selection of an 8-bit byte from the 1,048,576 available.
12
44
CE#
RP#
Input
Input
14
33
OE#
BYTE#
Input
Input
11, 10, 9, 8,
7, 6, 5, 4, 42,
41, 40, 39,
38, 37, 36,
35, 34, 3, 2
31
15, 17, 19,
21, 24, 26,
28, 30
16, 18, 20,
22, 25, 27,
29
1
A0-A18/
(A19)
Input
DQ15/
DQ0-
DQ7
DQ8-
DQ14
V
PP
Input/
(A - 1)
Input/
Output
Input/
Output
Supply
Data I/O: MSB of data when BYTE# = HIGH. Address Input: LSB Output
of address input when BYTE# = LOW during READ or WRITE operation.
Data I/Os: Data output during any READ operation or data input during a
WRITE. These pins are used to input commands to the CEL.
Data I/Os: Data output during any READ operation or data input during a
WRITE when BYTE# = HIGH. These pins are High-Z when BYTE# is LOW.
Write/Erase Supply Voltage: From a WRITE or ERASE CONFIRM until comple-
tion of the WRITE or ERASE, V
PP
must be at V
PPH
1
(3.3V), V
PPH
2
(5V) or V
PPH
3
(12V)
1
. V
PP
= “Don’t Care” during all other operations.
Power Supply: +3.3V ±0.3V.
Ground.
23
13, 32
V
CC
V
SS
Supply
Supply
NOTE:
1. For SmartVoltage-compatible production programming, 12V V
PP
is supported for a maximum of 100 cycles and may be
connected for up to 100 cumulative hours.
8Mb Smart 3 Boot Block Flash Memory
Q10.p65 – Rev.3/00
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
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