DC/DC converter
BP5250/BP5250-24
The BP5250/BP5250-24 are DC/DC converters for step-down that can drive PchFET using PWM system.
The voltage setting resistor and the combination of external power elements enable you to make any power
circuit to your liking. High-efficient DC/DC converter can be made easy by adding external components such
as I/O smoothing capacitor without designing circuit.
Applications
OA appliances(copy machine,personal computer, facsimile), AV appliances (car navigation, DVD etc.),
and industrial appliances.
Features
1) High power conversion(η=90% Vin=12V 5V/2A)
2) Power save pin(Leakage current at OFF mode : IR=10µAMAX)
3) Output voltage can be established from 1.5V to 9V in the VADJ pin.(For BP5250, however, output voltage is
limted by input voltage.)
4) With recovery type overcurrent protection function (Detection current can be established by the external
current detection resistance.)
5) Power circuit can be made easy by adding external smoothing capacitor and power element.
6) Reference voltage accuracy 1.25V±1%
Absolute maximum ratings (Ta=25°C)
Limits
Parameter
Input voltage
ESD endurance
Operating temperature range
Storage temperature range
Allowable max surface temperature
The power saving terminal voltage
Symbol
Vi
Vsurge
Topr
Tstg
Tfmax
V
CTL
24
BP5250
24
1
−40 ∼ +85
−50 ∼ +100
100
30
Unit
BP5250-24
30
V
kV
°C
°C
°C
V
Ambient temperature+The module self-heating
≤
Tfmax
Vi
≥
VCTL
DC
(EIAJ ED4701-1C-111A)
Condition
Recommended operating conditions (Ta=25°C)
Parameter
Input voltage
BP5250
BP5250-24
Symbol
Vi
Min.
8
20
Typ.
12
24
Max.
16
27
Unit
V
V
1/11
BP5250 / BP5250-24
Block diagram
CONTROL CIRCUIT
DRIVE CIRCUIT
OVER CURRENT
DETECTION CIRCUIT
1
V
CTL
2
Vi
3
SW
4
GND
5
IS
6
V
O
7
V
ADJ
Pin descriptions
Pin No.
1
2
3
4
5
6
7
Pin name
V
CTL
Vi
SW
GND
IS
Vo
V
ADJ
Function
Power save terminal.Setting the voltage on this terminal to Low or high impedance turns the
output OFF. Normally connect to Vi for use.
Input voltage terminal. Inserting a bypass capacitor of 0.1µF between this and pin 4 GND is
recommended.
Terminal to drive the external FET gate.
GND terminal. Connect the negative terminal of the I/O smoothing capacitor and the anode terminal
of the flywheel diode nearby.
Overcurrent detection terminal. The value of the resistor inserted between this and pin 6 sets the
output current capacity.
Output voltage monitor terminal.
Output voltage setting terminal. The values of the resistors inserted between this and pin 6 and
between this and GND set the output voltage capacity.
2/11
BP5250 / BP5250-24
Electrical characteristics (Unless otherwise noted, Vi=12V : BP5250, Vi=24V : BP5250-24, Ta=25°C)
Parameter
Output ADJ Pin voltage
Over current detection
off set voltage1
Over current detection
off set voltage2
CTL pin ON voltage
CTL pin OFF voltage
CTL sink current
Stand by current
Symbol
V
ADJ
V
LT1
V
LT2
V
CTLH
V
CTLL
I
CTL
I
STB
Min.
1.225
60
20
2
−
40
−
Typ.
1.25
68
28
−
−
50
0
Max.
1.275
76
36
−
1
70
10
Unit
V
mV
mV
V
V
µA
µA
Conditions
Test Circuit
Fig.1
Fig.2
Fig.2
Fig.3
Fig.3
Fig.3
Fig.3
VSW L→H
VSW L→H V
ADJ
=1.25V
VSW L→H V
ADJ
=0V
VSW H→L
VSW L→H
V
CTL
=5V
V
CTL
=0V
Measurement circuit
BP5250 / BP5250-24
V
CTL
1
Vi
2
SW
3
GND
4
IS
5
Vo
6
V
ADJ
7
Vi=12V : BP5250
Vi=24V : BP5250-24
V
CTL
1
BP5250 / BP5250-24
Vi
2
SW
3
GND
4
IS
5
Vo
6
V
ADJ
7
Vi=12V : BP5250
Vi=24V : BP5250-24
V
LT
L→H
V
SW
5V
Vi
V
ADJ
5V
Vi
L→H
V
SW
V
ADJ
Fig.1 Output ADJ terminal voltage measurement circuit
Over current detection off set voltage 1 : V
ADJ
=1.25V
Over current detection off set voltage 2 : V
ADJ
=0V
Fig.2 Over current detection off set voltage measurement circuit
BP5250 / BP5250-24
V
CTL
1
Vi
2
SW
3
GND
4
IS
5
Vo
6
V
ADJ
7
Vi=12V : BP5250
Vi=24V : BP5250-24
A
I
CTL
V
CTL
A
I
STB
V
SW
Vi
V
ADJ
1.25V
: V
CTL
=5V
: V
CTL
=0V
CTL sink current
Stad by current
Fig.3 Control terminal voltage sink current ·
Stand by sink current measurement circuit
3/11
BP5250 / BP5250-24
Application example
(1) Application circuit example is shown in the Fig.4.
R1 : Over-current detection resistance R1=0.068/I
(0.068V : offset voltage)
Overcurrent protection characteristic
at R1=27mΩ is shown below.
BP5250 / BP5250-24
V
CTL
1
Vi
2
SW
3
Q1
GND
4
IS
5
L1
R1
22µH 27mΩ
C2
680µF/16V
Vo
6
V
ADJ
Output voltage [v]
6.0
5.0
4.0
3.0
2.0
1.0
0
I
0
500
1000
1500
2000
Output current [mA]
2500
BP5250 over-current protection
characteristic (Vin=12V)
7
R3 : 30kΩ
C3
Vout
R2
10kΩ
C4
Vin
C1
680µF/25V
SD1
Fig.4
∗Application
Input voltage 12V
Output current 2A
Output voltage 5V
Q1 : 2SJ529S/Hitachi
SD : RB050L-40/ROHM
L1 : CDRH124-220L/Sumida
C1 : 680µF/25V
(ZL series)
/Rubycon
C2 : 680µF/10V
(ZL series)
/Rubycon
C3 : 0.1µF/16V
C4 : 0.1µF/25V
R2, R3 : Outpur voltage
Establishment example
establishment resistance
Vo(V) R2(Ω) R3(Ω)
Vo=VADJ
×
(1+R3/R2)
(R2+R3≤55kΩ)
8.0
5.0
3.3
2.5
1.5
3.3k
10k
20k
10k
10k
18k
30k
33k
10k
2k
· There is a posibility that the C1 exceeds the allowable ripple current. Note the allowable ripple
current of the capacitor to be used.
· R2+R3≤55KΩ is recommended for R2,3 to make the most of output voltage accuracy.
· Output voltage range is limited by input voltage. Please refer to the Fig.8.
(2) When the load current is increased.
It is possible by arrangement in a parallel connecting
Q1, 2 and SD1,2
(3) When the power saving function is used.
The output is off when the V
CTL
pin is set to the
Low or high-impedance.
BP5250 / BP5250-24
V
CTL
1
Vi
2
C4
Q1
Vin
C1
SD1,2
Q2
C2
L1
R1
SW
3
GND
4
IS
5
Vo
6
V
ADJ
7
R3
C3
Vout
R2
Vin
V
CTL
1
BP5250 / BP5250-24
Vi
2
SW
SW
3
Q1
GND
4
IS
5
Vo
6
V
ADJ
7
R3
C4
L1
R1
C2
C3
Vout
R2
C1
SD1
Fig.5
Fig.6
· When Q1 and Q2 are connected parallel, use of a
device with small gate capacity is recommended.
Large gate capacity reduces the switching speed,
which may cause a larger FET loss, exceeding
the allowable loss value.
· When 2SJ529S is connected parallel, the rated load
current 3A is the maximum atVi=12V,Vo=5V
4/11
BP5250 / BP5250-24
Output voltage establishment range
Output voltage establishment range is changed by input voltage.Please refer to the Fig.8.
Vi−Vo characteristic
30
Output voltage
establishment [v]
25
20
15
10
5
0
6
BP5250
8 10 12 14 16 18 20 22 24 26 28 30
Vi [V]
9V
17V
24V
BP5250-24
1.5V
Fig.8
Caution note for operation
(1) Output voltage establishment range is changed by input voltage.Please refer to the Fig.8.
(2) Layout of external parts may significantly change the output spike noise or characteristics or cause abnomal
oscillation and temperature increase. Note the following for layout.
· Provide the input smoothing electroytic capacitor close to the FET source and pin 2 of the module.
· Provide the output smoothing electrolytic capacitor close to pin 6 of the module together with the
current detection resistor
· Large current may run into the coil, current detection resistor and output through the FET source-
drain.Try to use a solid pattern as much as possible.
· FET drain, coil and flywheel diode may generate heat by power loss. Try to use a solid pattern so that the
heat may be released. Measure a rise in temperature of each element and make sure that it is not
abnormal.
· Provide the negative terminal of the I/O smoothing capacitor and anode terminal of the flywheel diode
close to GND pin 4 of the module.
· Connect the negative terminal of the I/O smoothing electrolytic capacitor and anode terminal of the
flywheel diode nearby.
(3) Output load may cause large ripple current in the I/O smoothing electrolytic capacitor. Note the allowable
ripple current of the capacitor to be used.
(4) As the output smoothing electrolytic capacitor, one with especially low impedance is recommended for
suppresing output ripple voltage. Select a capacitor suited for the use.
(5) Please be sure to use protection circuit function.(R1 should not be 0Ω.)
Output voltage establishment and application circuit example
∗Application
example
Input voltage 12V
Output voltage 5V
Q1 : 2SJ529S/hitachi
SD : RB050L-40/ROHM
L1 : CDRH124-220L/Sumida
C1 : 680µF/25V
(ZL seried)
/Rubycon
C2 : 680µF/16V
(ZL series)
/Rubycon
C3 : 0.1µF/16V/ROHM
C4 : 0.1µF/25V/ROHM
BP5250-BP5250-24
V
CTL
1
Vi
2
SW
3
Q1
GND
4
IS
5
Vo
6
V
ADJ
7
R3
C4
Vin
C1
L1
R1
C2
C3
Vout
R2
R1 : 27mΩ/SUSUMU
R2 : 10kΩ/ROHM
R3 : 30kΩ/ROHM
SD1
Fig.9
5/11
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