WEDPN8M64VR-XBX
8Mx64 Registered Synchronous DRAM
FEATURES
!
Registered for enhanced performance of bus speeds
of 66 MHz and 100 MHz
!
Package:
• 219 Plastic Ball Grid Array (PBGA), 32 x 25mm
!
Single 3.3V ±0.3V power supply
!
Fully synchronous; all signals registered on positive edge
of system clock cycle
!
Internal pipelined operation; column address can be
changed every clock cycle
!
Internal banks for hiding row access/precharge
!
Programmable Burst length 1,2,4,8 or full page
!
4096 refresh cycles
!
Commercial, Industrial and Military Temperature Ranges
!
Organized as 8M x 64
• User configurable as 2x8Mx32 or 4x8Mx16
!
Weight: WEDPN8M64VR-XBX - 2.5 grams typical
GENERAL DESCRIPTION
The 64MByte (512Mb) SDRAM is a high-speed CMOS, dy-
namic random-access memory using 4 chips containing
134,217,728 bits. Each chip is internally configured as a
quad-bank DRAM with a synchronous interface. Each of the
chip’s 33,554,432-bit banks is organized as 4,096 rows by
512 columns by 16 bits. The MCP also incorporates two
16-bit universal bus drivers for input control signals and ad-
dress.
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for a pro-
grammed number of locations in a programmed sequence.
Accesses begin with the registration of an ACTIVE com-
mand, which is then followed by a READ or WRITE com-
mand. The address bits registered coincident with the AC-
TIVE command are used to select the bank and row to be
accessed (BA0, BA1 select the bank; A0-11 select the row).
The address bits registered coincident with the READ or
WRITE command are used to select the starting column lo-
cation for the burst access.
The SDRAM provides for programmable READ or WRITE burst
lengths of 1, 2, 4 or 8 locations, or the full page, with a
burst terminate option. An AUTO PRECHARGE function may
be enabled to provide a self-timed row precharge that is
initiated at the end of the burst sequence.
The 512Mb SDRAM uses an internal pipelined architecture
to achieve high-speed operation. This architecture is com-
patible with the 2n rule of prefetch architectures, but it also
allows the column address to be changed on every clock
cycle to achieve a high-speed, fully random access.
Precharging one bank while accessing one of the other three
banks will hide the precharge cycles and provide seam-
less, high-speed, random-access operation.
The 512Mb SDRAM is designed to operate in 3.3V, low-
power memory systems. An auto refresh mode is provided,
along with a power-saving, power-down mode.
All inputs and outputs are LVTTL compatible. SDRAMs offer
substantial advances in DRAM operating performance, in-
cluding the ability to synchronously burst data at a high data
rate with automatic column-address generation, the ability
to interleave between internal banks in order to hide
precharge time and the capability to randomly change col-
umn addresses on each clock cycle during a burst access.
BENEFITS
!
41% SPACE SAVINGS
!
Reduced part count
!
Reduced trace lengths for lower parasitic capacitance
!
Glueless connection to memory controller/PCI bridge
!
Laminate interposer for optimum TCE match
!
Suitable for hi-reliability applications
!
Upgradeable to 16M x 64 density (contact factory for
information)
* This data sheet describes a product that is subject to change without notice.
November 2003 Rev. 4
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WEDPN8M64VR-XBX
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IG
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P
IN
C
ONFIGURATION
T
OP
V
IEW
NOTE: DNU = Do Not Use; to be left unconnected for future upgrades.
NC = Not Connected Internally.
White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520
2
WEDPN8M64VR-XBX
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F
UNCTIONAL
B
LOCK
D
IAGRAM
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White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WEDPN8M64VR-XBX
FUNCTIONAL DESCRIPTION
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for a pro-
grammed number of locations in a programmed sequence.
Accesses begin with the registration of an ACTIVE com-
mand which is then followed by a READ or WRITE com-
mand. The address bits registered coincident with the AC-
TIVE command are used to select the bank and row to be
accessed (BA0 and BA1 select the bank, A0-11 select the
row). The address bits (A0-8) registered coincident with
the READ or WRITE command are used to select the start-
ing column location for the burst access.
Prior to normal operation, the SDRAM must be initialized.
The following sections provide detailed information cover-
ing device initialization, register definition, command de-
scriptions and device operation.
ating mode and a write burst mode, as shown in Figure 3.
The Mode Register is programmed via the LOAD MODE REG-
ISTER command and will retain the stored information until
it is programmed again or the device loses power.
Mode register bits M0-M2 specify the burst length, M3
specifies the type of burst (sequential or interleaved), M4-
M6 specify the CAS latency, M7 and M8 specify the oper-
ating mode, M9 specifies the WRITE burst mode, and M10
and M11 are reserved for future use.
The Mode Register must be loaded when all banks are idle,
and the controller must wait the specified time before initi-
ating the subsequent operation. Violating either of these
requirements will result in unspecified operation.
BURST LENGTH
Read and write accesses to the SDRAM are burst oriented,
with the burst length being programmable, as shown in Fig-
ure 3. The burst length determines the maximum number of
column locations that can be accessed for a given READ or
WRITE command. Burst lengths of 1, 2, 4 or 8 locations are
available for both the sequential and the interleaved burst
types, and a full-page burst is available for the sequential
type. The full-page burst is used in conjunction with the
BURST TERMINATE command to generate arbitrary burst
lengths.
Reserved states should not be used, as unknown opera-
tion or incompatibility with future versions may result.
When a READ or WRITE command is issued, a block of col-
umns equal to the burst length is effectively selected. All
accesses for that burst take place within this block, mean-
ing that the burst will wrap within the block if a boundary is
reached. The block is uniquely selected by A1-8 when the
burst length is set to two; by A2-8 when the burst length is
set to four; and by A3-8 when the burst length is set to
eight. The remaining (least significant) address bit(s) is (are)
used to select the starting location within the block. Full-
page bursts wrap within the page if the boundary is reached.
INITIALIZATION
SDRAMs must be powered up and initialized in a predefined
manner. Operational procedures other than those speci-
fied may result in undefined operation. Once power is ap-
plied to VDD and VDDQ (simultaneously) and the clock is
stable (stable clock is defined as a signal cycling within tim-
ing constraints specified for the clock pin), the SDRAM re-
quires a 100µs delay prior to issuing any command other
than a COMMAND INHIBIT or a NOP. Starting at some point
during this 100µs period and continuing at least through
the end of this period, COMMAND INHIBIT or NOP com-
mands should be applied.
Once the 100µs delay has been satisfied with at least one
COMMAND INHIBIT or NOP command having been applied,
a PRECHARGE command should be applied. All banks must
be precharged, thereby placing the device in the all banks
idle state.
Once in the idle state, two AUTO REFRESH cycles must be
performed. After the AUTO REFRESH cycles are complete, the
SDRAM is ready for Mode Register programming. Because the
Mode Register will power up in an unknown state, it should
be loaded prior to applying any operational command.
BURST TYPE
REGISTER DEFINITION
MODE REGISTER
The Mode Register is used to define the specific mode of
operation of the SDRAM. This definition includes the selec-
tion of a burst length, a burst type, a CAS latency, an oper-
White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520
4
Accesses within a given burst may be programmed to be
either sequential or interleaved; this is referred to as the
burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by
the burst length, the burst type and the starting column
address, as shown in Table 1.
WEDPN8M64VR-XBX
T
ABLE
1 - B
URST
D
EFINITION
Burst
Length
2
Starting Column
Address
A0
0
1
A1 A0
0
0
0
1
1
0
1
1
A2 A1 A0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
n = A0-9/8/7
(location 0-y)
Order of Accesses Within a Burst
Type = Sequential
0-1
1-0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
Cn, Cn + 1, Cn + 2
Cn + 3, Cn + 4...
…Cn - 1,
Cn…
Type = Interleaved
0-1
1-0
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
Not Supported
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IG
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M
ODE
R
EGISTER
D
EFINITION
4
8
Full
Page
(y)
NOTES:
1. For full-page accesses: y = 512.
2. For a burst length of two, A1-8 select the block-of-two burst; A0 selects the
starting column within the block.
3. For a burst length of four, A2-8 select the block-of-four burst; A0-1 select the
starting column within the block.
4. For a burst length of eight, A3-8 select the block-of-eight burst; A0-2 select
the starting column within the block.
5. For a full-page burst, the full row is selected and A0-8 select the starting
column.
6. Whenever a boundary of the block is reached within a given sequence
above, the following access wraps within the block.
7. For a burst length of one, A0-8 select the unique column to be accessed, and
Mode Register bit M3 is ignored.
5
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