SPANSION Flash Memory
Data Sheet
TM
September 2003
TM
This document specifies SPANSION memory products that are now offered by both Advanced Micro Devices and
Fujitsu. Although the document is marked with the name of the company that originally developed the specification,
these products will be offered to customers of both AMD and Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a SPANSION
revisions will occur when appropriate, and changes will be noted in a revision summary.
TM
product. Future routine
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with "Am" and "MBM". To order these
products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about SPANSION
solutions.
TM
memory
FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-20900-1E
PAGE MODE FLASH MEMORY
CMOS
96M (6M
×
16) BIT
MBM29QM96DF-
65/80
s
GENERAL DESCRIPTION
The MBM29QM96DF is 96M-bit, 3.0 V-only Page mode and dual operation Flash memory organized as 6M words
by 16 bits. The device is offered in a 80-ball FBGA package. This device is designed to be programmed in-system
with the standard system 3.0 V Vcc supply. 12.0 V Vpp and 5.0 V Vcc are not required for program or erase
operations. The device can also be reprogrammed in standard EPROM programmers.
(Continued)
s
PRODUCT LINEUP
Part No.
Ordering Part Number Suffix
V
CC
(V)
V
CCQ
(V)
Max Random Address Access Time (ns)
Max Page Address Access Time (ns)
Max CE Access Time (ns)
Max OE Access Time (ns)
65
2.7 to 3.1
V
CC
65
25
65
25
MBM29QM96DF
80
2.7 to 3.1
1.65 to V
CC
80
30
80
30
s
PACKAGE
80-ball plastic FBGA
(BGA-80P-M03)
MBM29QM96DF
-65/80
(Continued)
The device provides truly high performance non-volatile Flash memory solution. The device offers fast page
access times of 25 ns with random access times of 65 ns , allowing operation of high-speed microprocessors
without wait states. To eliminate bus contention the device has separate chip enable (CE), write enable (WE),
and output enable (OE) controls. The page size is 8 words.
The dual operation function provides simultaneous operation by dividing the memory space into four banks. The
device can improve overall system performance by allowing a host system to program or erase in one bank,
then immediately and simultaneously read from the other bank with zero latency. This releases the system from
waiting for the completion of program or erase operations.
The device is command set compatible with JEDEC standard E
2
PROMs. Commands are written to the command
register using standard microprocessor write timings. Register contents serve as input to an internal state-
machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and
data needed for the program and erase operations. Reading data out of the device is similar to reading from 5.0
V and 12.0 V Flash or EPROM devices.
The device is programmed by executing the program command sequence. This will invoke the Embedded
Program Algorithm
TM
which is an internal algorithm that automatically times the program pulse widths and verifies
proper cell margins. Typically, each 32K words sector can be programmed and verified in about 0.3 seconds.
Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase
Algorithm
TM
which is an internal algorithm that automatically preprograms the array if it is not already programmed
before executing the erase operation. During erase, the device automatically times the erase pulse widths and
verifies proper cell margins.
Any individual sector is typically erased and verified in 0.5 second. (If already preprogrammed.)
The device also features a sector erase architecture. The sector mode allows each sector to be erased and
reprogrammed without affecting other sectors. The device is erased when shipped from the factory.
The Enhanced V
I/O
(V
CCQ
) feature allows the output voltage generated on the device to be determined based on
the V
I/O
level. This feature allows this device to operate in the 1.8 V I/O environment, driving and receiving signals
to and from other 1.8 V devices on the same bus.
The device features single 3.0 V power supply operation for both read and write functions. Internally generated
and regulated voltages are provided for the program and erase operations. A low V
CC
detector automatically
inhibits program and erase operations on the loss of power. The end of program or erase is detected by Data
Polling of DQ
7
, by the Toggle Bit feature on DQ
6
, output pin. Once the end of a program or erase cycle has been
completed, the device internally resets to the read mode.
Fujitsu’s Flash technology combines years of Flash memory manufacturing experience to produce the highest
levels of quality, reliability, and cost effectiveness. The device memory electrically erases all bits within a sector
simultaneously via Fowler-Nordhiem tunneling. The words are programmed one word at a time using the EPROM
programming mechanism of hot electron injection.
2
MBM29QM96DF
-65/80
s
FEATURES
• 0.17
µ
m Process Technology
• Single 3.0 V Read, Program and Erase
Minimized system level power requirements
• Simultaneous Read/Write (Program and Erase) Operations (Dual Bank)
• FlexBank
TM
*
1
Bank A: 12 Mbit (4K words
×
8 and 32K words
×
23)
Bank B: 36 Mbit (32K words
×
72)
Bank C: 36 Mbit (32K words
×
72)
Bank D: 12 Mbit (4K words
×
8 and 32K words
×
23)
• Enhanced V
I/O
(V
CCQ
) Feature
Input/Output voltage generated on the device is determined based on the V
I/O
level
• High Performance Page Mode
25 ns maximum page access time (65 ns random access time)
• 8 Words Page Size
• Compatible with JEDEC-Standard Commands
Uses same software commands as E
2
PROMs
• Minimum 100,000 Program/Erase Cycles
• Sector Erase Architecture
Eight 4K words, a hundred ninety 32K words, eight 4K words sectors
Any combination of sectors can be concurrently erased. Also supports full chip erase
• Dual Boot Block
16 by 4K words bootblock sectors, 8 at the top of the address range and 8 at the bottom of the address range
• HiddenROM Region
256 byte of HiddenROM, accessible through a new “HiddenROM Enable” command sequence
Factory serialized and protected to provide a secure electronic serial number (ESN)
• WP/ACC Input Pin
At V
IL
, allows protection of “outermost” 2
×
4K words on both ends of boot sectors, regardless of sector
protection/unprotection status
At V
IH
, allows removal of boot sector protection
At V
ACC
, increases program performance
• Embedded Erase
TM
*
2
Algorithms
Automatically preprograms and erases the chip or any sector
• Embedded Program
TM
*
2
Algorithms
Automatically programs and verifies data at specified address
• Data Polling and Toggle Bit Feature for detection of program or erase cycle completion
• Ready/Busy Output (RY/BY)
Hardware method for detection of program or erase cycle completion
• Automatic Sleep Mode
When addresses remain stable, the device automatically switches itself to low power mode.
• Low V
CC
Write Inhibit
≤
V
LKO
• Program Suspend/Resume
Suspends the program operation to allow a read in another word
• Erase Suspend/Resume
Suspends the erase operation to allow a read data and/or program in another sector within the same device
(Continued)
*1 : FlexBank
TM
is a trademark of Fujitsu Limited.
*2 : Embedded Erase
TM
and Embedded Program
TM
are trademarks of Advanced Micro Devices, Inc.
3
MBM29QM96DF
-65/80
(Continued)
• In accordance with CFI (Common Flash Memory Interface)
• Hardware Reset Pin (RESET)
Hardware method to reset the device for reading array data
• New Sector Protection
Persistent Sector Protection
Password Sector Protection
4
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