Changes to Ordering Guide ............................................................27
10/02—Revision 0: Initial Version
Rev. B | Page 2 of 28
AD5280/AD5282
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
V
DD
= +15 V, V
SS
= 0 V or V
DD
= +5 V, V
SS
= −5 V; V
LOGIC
= 5 V, V
A
= +V
DD
, V
B
= 0 V; −40°C < T
A
< +85°C, unless otherwise noted.
Table 1.
Parameter
Symbol
Conditions
DC CHARACTERISTICS–RHEOSTAT MODE
Resistor Differential NL
2
R-DNL
R
WB
, V
A
= NC
2
Resistor Nonlinearity
R-INL
R
WB
, V
A
= NC
Nominal Resistor Tolerance
3
ΔR
AB
T
A
= 25°C
6
V
AB
= V
DD
, wiper = no connect
Resistance Temperature
(∆R
AB
/R
AB
)/∆T x 10
Coefficient
Wiper Resistance
R
W
I
W
= V
DD
/R, V
DD
= 3 V or 5 V
DC CHARACTERISTICS–POTENTIOMETER DIVIDER MODE (specifications apply to all VRs)
Resolution
N
Integral Nonlinearity
4
INL
4
Differential Nonlinearity
DNL
Code = 0x80
(∆V
W
/V
W
)/∆T x 10
6
Voltage Divider Temperature
Coefficient
Full-Scale Error
V
WFSE
Code = 0xFF
Zero-Scale Error
V
WZSE
Code = 0x00
RESISTOR TERMINALS
Voltage Range
5
V
A
, V
B
, V
W
6
Capacitance A, B
C
A
, C
B
f = 5 MHz, measured to GND,
Code = 0x80
6
Capacitance W
C
W
f = 1 MHz, measured to GND,
Code = 0x80
Common-Mode Leakage
I
CM
V
A
= V
B
= V
W
Shutdown Current
I
SHDN
DIGITAL INPUTS AND OUTPUTS
Input Logic High
V
IH
Input Logic Low
V
IL
Output Logic High (O
1
, O
2
)
V
IH
Output Logic Low (O
1
, O
2
)
V
IL
Input Current
I
IL
V
IN
= 0 V or 5 V
Input Capacitance
6
C
IL
POWER SUPPLIES
Logic Supply
V
LOGIC
Power Single-Supply Range
V
DD RANGE
V
SS
= 0 V
Power Dual-Supply Range
V
DD/SS RANGE
Logic Supply Current
I
LOGIC
V
LOGIC
= 5 V
Positive Supply Current
I
DD
V
IH
= 5 V or V
IL
= 0 V
Negative Supply Current
I
SS
7
Power Dissipation
P
DISS
V
IH
= 5 V or V
IL
= 0 V, V
DD
= +5 V, V
SS
= −5
V
Power Supply Sensitivity
PSS
DYNAMIC CHARACTERISTICS
6, 8, 9
Bandwidth −3 dB
BW_20K
R
AB
= 20 kΩ, Code = 0x80
BW_50K
R
AB
= 50 kΩ, Code = 0x80
BW_200K
R
AB
= 200 kΩ, Code = 0x80
Min
−1
−1
−30
Typ
1
±1/4
±1/4
30
60
8
−1
−1
150
Max
+1
+1
+30
Unit
LSB
LSB
%
ppm/°C
Ω
Bits
LSB
LSB
ppm/°C
LSB
LSB
V
pF
pF
nA
μA
V
V
V
V
μA
pF
V
V
V
μA
μA
μA
mW
%/%
kHz
kHz
kHz
±1/4
±1/4
5
−1
+1
+1
+1
−2
0
V
SS
0
+2
V
DD
25
55
1
5
0.7 × V
L
0
4.9
V
L
+ 0.5
0.3 × V
L
0.4
±1
5
2.7
4.5
±4.5
0.1
0.1
0.2
0.002
310
150
35
V
DD
16.5
±5.5
60
1
1
0.3
0.01
Rev. B | Page 3 of 28
AD5280/AD5282
Parameter
Total Harmonic Distortion
V
W
Settling Time
Crosstalk
Symbol
THD
W
t
S
CT
Conditions
V
A
= 1 V rms, R
AB
= 20 kΩ
V
B
= 0 V dc, f = 1 kHz
V
A
= 5 V, V
B
= 5 V, ±1 LSB error band
V
A
= V
DD
, V
B
= 0 V, measure V
W1
with
adjacent RDAC making full-scale
code change
Measure V
W1
with V
W2
= 5 V p-p @ f =
10 kHz
R
WB
= 20 kΩ, f = 1 kHz
Min
Typ
1
0.014
5
15
Max
Unit
%
μs
nV-s
Analog Crosstalk
CTA
−62
18
dB
nV/√Hz
400
kHz
μs
μs
μs
μs
μs
0.9
300
300
μs
ns
ns
ns
μs
Resistor Noise Voltage
e
N_WB
INTERFACE TIMING CHARACTERISTICS (applies to all parts)
6, 10, 11
SCL Clock Frequency
f
SCL
t
1
t
BUF
Bus Free Time Between
Stop and Start
t
2
t
HD:STA
Hold Time (Repeated
After this period, the first clock pulse
Start)
is generated
t
LOW
Low Period of SCL Clock
t
3
t
HIGH
High Period of SCL Clock
t
4
t
5
t
SU:STA
Setup Time for Start
Condition
t
HD:DAT
Data Hold Time
t
6
t
SU:DAT
Data Setup Time
t
7
t
8
t
F
Fall Time of Both SDA and
SCL Signals
t
9
t
R
Rise Time of Both SDA and
SCL Signals
t
10
t
SU:STO
Setup Time for STOP
Condition
1
2
0
1.3
0.6
1.3
0.6
0.6
0
100
0.6
Typicals represent average readings at 25°C, V
DD
= +5 V, V
SS
=
−5
V.
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3
V
AB
= V
DD
, wiper (V
W
) = no connect.
4
INL and DNL are measured at V
W
with the RDAC configured as a potentiometer divider similar to a voltage output DAC. V
A
= V
DD
and V
B
= 0 V. DNL specification limits
of
±1
LSB maximum are guaranteed monotonic operating conditions.
5
Resistor Terminal A, Resistor Terminal B, and Wiper Terminal W have no limitations on polarity with respect to each other.
6
Guaranteed by design and not subject to production test.
7
P
DISS
is calculated from (I
DD
× V
DD
). CMOS logic level inputs result in minimum power dissipation.
8
Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest
bandwidth. The highest R value results in the minimum overall power consumption.
9
All dynamic characteristics use V
DD
= 5 V.
10
See timing diagram (Figure 3) for location of measured values.
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